Caches.py revision 11763:302c6b957854 
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
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8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
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11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
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17# modification, are permitted provided that the following conditions are
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27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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38#
39# Authors: Lisa Hsu
40
41from m5.defines import buildEnv
42from m5.objects import *
43
44# Base implementations of L1, L2, IO and TLB-walker caches. There are
45# used in the regressions and also as base components in the
46# system-configuration scripts. The values are meant to serve as a
47# starting point, and specific parameters can be overridden in the
48# specific instantiations.
49
50class L1Cache(Cache):
51    assoc = 2
52    tag_latency = 2
53    data_latency = 2
54    response_latency = 2
55    mshrs = 4
56    tgts_per_mshr = 20
57
58class L1_ICache(L1Cache):
59    is_read_only = True
60    # Writeback clean lines as well
61    writeback_clean = True
62
63class L1_DCache(L1Cache):
64    pass
65
66class L2Cache(Cache):
67    assoc = 8
68    tag_latency = 20
69    data_latency = 20
70    response_latency = 20
71    mshrs = 20
72    tgts_per_mshr = 12
73    write_buffers = 8
74
75class IOCache(Cache):
76    assoc = 8
77    tag_latency = 50
78    data_latency = 50
79    response_latency = 50
80    mshrs = 20
81    size = '1kB'
82    tgts_per_mshr = 12
83
84class PageTableWalkerCache(Cache):
85    assoc = 2
86    tag_latency = 2
87    data_latency = 2
88    response_latency = 2
89    mshrs = 10
90    size = '1kB'
91    tgts_per_mshr = 12
92
93    # the x86 table walker actually writes to the table-walker cache
94    if buildEnv['TARGET_ISA'] == 'x86':
95        is_read_only = False
96    else:
97        is_read_only = True
98        # Writeback clean lines as well
99        writeback_clean = True
100