xref: /gem5/configs/common/Caches.py

# Copyright (c) 2012 ARM Limited
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# Authors: Lisa Hsu

from m5.objects import *

# Base implementations of L1, L2, IO and TLB-walker caches. There are
# used in the regressions and also as base components in the
# system-configuration scripts. The values are meant to serve as a
# starting point, and specific parameters can be overridden in the
# specific instantiations.

class L1Cache(BaseCache):
    assoc = 2
    hit_latency = 2
    response_latency = 2
    block_size = 64
    mshrs = 4
    tgts_per_mshr = 20
    is_top_level = True

class L2Cache(BaseCache):
    assoc = 8
    block_size = 64
    hit_latency = 20
    response_latency = 20
    mshrs = 92
    tgts_per_mshr = 16
    write_buffers = 8

class IOCache(BaseCache):
    assoc = 8
    block_size = 64
    hit_latency = 50
    response_latency = 50
    mshrs = 20
    size = '1kB'
    tgts_per_mshr = 12
    forward_snoops = False
    is_top_level = True

class PageTableWalkerCache(BaseCache):
    assoc = 2
    block_size = 64
    hit_latency = 2
    response_latency = 2
    mshrs = 10
    size = '1kB'
    tgts_per_mshr = 12
    is_top_level = True