CacheConfig.py revision 8056 
1# Copyright (c) 2010 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
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5# modification, are permitted provided that the following conditions are
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13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26#
27# Authors: Lisa Hsu
28
29# Configure the M5 cache hierarchy config in one place
30#
31
32import m5
33from m5.objects import *
34from Caches import *
35
36def config_cache(options, system):
37    if options.l2cache:
38        system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc)
39        system.tol2bus = Bus()
40        system.l2.cpu_side = system.tol2bus.port
41        system.l2.mem_side = system.membus.port
42        system.l2.num_cpus = options.num_cpus
43
44    for i in xrange(options.num_cpus):
45        if options.caches:
46            icache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc)
47            dcache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc)
48            if buildEnv['TARGET_ISA'] == 'x86':
49                system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
50                                                      PageTableWalkerCache(),
51                                                      PageTableWalkerCache())
52            else:
53                system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
54        if options.l2cache:
55            system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
56        else:
57            system.cpu[i].connectAllPorts(system.membus)
58
59    return system
60