CacheConfig.py revision 13811:88827de8fced 
1# Copyright (c) 2012-2013, 2015-2016 ARM Limited
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13# Copyright (c) 2010 Advanced Micro Devices, Inc.
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38#
39# Authors: Lisa Hsu
40
41# Configure the M5 cache hierarchy config in one place
42#
43
44from __future__ import print_function
45from __future__ import absolute_import
46
47import m5
48from m5.objects import *
49from .Caches import *
50
51def config_cache(options, system):
52    if options.external_memory_system and (options.caches or options.l2cache):
53        print("External caches and internal caches are exclusive options.\n")
54        sys.exit(1)
55
56    if options.external_memory_system:
57        ExternalCache = ExternalCacheFactory(options.external_memory_system)
58
59    if options.cpu_type == "O3_ARM_v7a_3":
60        try:
61            import cores.arm.O3_ARM_v7a as core
62        except:
63            print("O3_ARM_v7a_3 is unavailable. Did you compile the O3 model?")
64            sys.exit(1)
65
66        dcache_class, icache_class, l2_cache_class, walk_cache_class = \
67            core.O3_ARM_v7a_DCache, core.O3_ARM_v7a_ICache, \
68            core.O3_ARM_v7aL2, \
69            core.O3_ARM_v7aWalkCache
70    elif options.cpu_type == "HPI":
71        try:
72            import cores.arm.HPI as core
73        except:
74            print("HPI is unavailable.")
75            sys.exit(1)
76
77        dcache_class, icache_class, l2_cache_class, walk_cache_class = \
78            core.HPI_DCache, core.HPI_ICache, core.HPI_L2, core.HPI_WalkCache
79    else:
80        dcache_class, icache_class, l2_cache_class, walk_cache_class = \
81            L1_DCache, L1_ICache, L2Cache, None
82
83        if buildEnv['TARGET_ISA'] == 'x86':
84            walk_cache_class = PageTableWalkerCache
85
86    # Set the cache line size of the system
87    system.cache_line_size = options.cacheline_size
88
89    # If elastic trace generation is enabled, make sure the memory system is
90    # minimal so that compute delays do not include memory access latencies.
91    # Configure the compulsory L1 caches for the O3CPU, do not configure
92    # any more caches.
93    if options.l2cache and options.elastic_trace_en:
94        fatal("When elastic trace is enabled, do not configure L2 caches.")
95
96    if options.l2cache:
97        # Provide a clock for the L2 and the L1-to-L2 bus here as they
98        # are not connected using addTwoLevelCacheHierarchy. Use the
99        # same clock as the CPUs.
100        system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
101                                   size=options.l2_size,
102                                   assoc=options.l2_assoc)
103
104        system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
105        system.l2.cpu_side = system.tol2bus.master
106        system.l2.mem_side = system.membus.slave
107
108    if options.memchecker:
109        system.memchecker = MemChecker()
110
111    for i in range(options.num_cpus):
112        if options.caches:
113            icache = icache_class(size=options.l1i_size,
114                                  assoc=options.l1i_assoc)
115            dcache = dcache_class(size=options.l1d_size,
116                                  assoc=options.l1d_assoc)
117
118            # If we have a walker cache specified, instantiate two
119            # instances here
120            if walk_cache_class:
121                iwalkcache = walk_cache_class()
122                dwalkcache = walk_cache_class()
123            else:
124                iwalkcache = None
125                dwalkcache = None
126
127            if options.memchecker:
128                dcache_mon = MemCheckerMonitor(warn_only=True)
129                dcache_real = dcache
130
131                # Do not pass the memchecker into the constructor of
132                # MemCheckerMonitor, as it would create a copy; we require
133                # exactly one MemChecker instance.
134                dcache_mon.memchecker = system.memchecker
135
136                # Connect monitor
137                dcache_mon.mem_side = dcache.cpu_side
138
139                # Let CPU connect to monitors
140                dcache = dcache_mon
141
142            # When connecting the caches, the clock is also inherited
143            # from the CPU in question
144            system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
145                                                  iwalkcache, dwalkcache)
146
147            if options.memchecker:
148                # The mem_side ports of the caches haven't been connected yet.
149                # Make sure connectAllPorts connects the right objects.
150                system.cpu[i].dcache = dcache_real
151                system.cpu[i].dcache_mon = dcache_mon
152
153        elif options.external_memory_system:
154            # These port names are presented to whatever 'external' system
155            # gem5 is connecting to.  Its configuration will likely depend
156            # on these names.  For simplicity, we would advise configuring
157            # it to use this naming scheme; if this isn't possible, change
158            # the names below.
159            if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
160                system.cpu[i].addPrivateSplitL1Caches(
161                        ExternalCache("cpu%d.icache" % i),
162                        ExternalCache("cpu%d.dcache" % i),
163                        ExternalCache("cpu%d.itb_walker_cache" % i),
164                        ExternalCache("cpu%d.dtb_walker_cache" % i))
165            else:
166                system.cpu[i].addPrivateSplitL1Caches(
167                        ExternalCache("cpu%d.icache" % i),
168                        ExternalCache("cpu%d.dcache" % i))
169
170        system.cpu[i].createInterruptController()
171        if options.l2cache:
172            system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
173        elif options.external_memory_system:
174            system.cpu[i].connectUncachedPorts(system.membus)
175        else:
176            system.cpu[i].connectAllPorts(system.membus)
177
178    return system
179
180# ExternalSlave provides a "port", but when that port connects to a cache,
181# the connecting CPU SimObject wants to refer to its "cpu_side".
182# The 'ExternalCache' class provides this adaptation by rewriting the name,
183# eliminating distracting changes elsewhere in the config code.
184class ExternalCache(ExternalSlave):
185    def __getattr__(cls, attr):
186        if (attr == "cpu_side"):
187            attr = "port"
188        return super(ExternalSlave, cls).__getattr__(attr)
189
190    def __setattr__(cls, attr, value):
191        if (attr == "cpu_side"):
192            attr = "port"
193        return super(ExternalSlave, cls).__setattr__(attr, value)
194
195def ExternalCacheFactory(port_type):
196    def make(name):
197        return ExternalCache(port_data=name, port_type=port_type,
198                             addr_ranges=[AllMemory])
199    return make
200