CacheConfig.py revision 9815
19793Sakash.bagdia@arm.com# Copyright (c) 2012-2013 ARM Limited 29522SAndreas.Sandberg@ARM.com# All rights reserved 39522SAndreas.Sandberg@ARM.com# 49522SAndreas.Sandberg@ARM.com# The license below extends only to copyright in the software and shall 59522SAndreas.Sandberg@ARM.com# not be construed as granting a license to any other intellectual 69522SAndreas.Sandberg@ARM.com# property including but not limited to intellectual property relating 79522SAndreas.Sandberg@ARM.com# to a hardware implementation of the functionality of the software 89522SAndreas.Sandberg@ARM.com# licensed hereunder. You may use the software subject to the license 99522SAndreas.Sandberg@ARM.com# terms below provided that you ensure that this notice is replicated 109522SAndreas.Sandberg@ARM.com# unmodified and in its entirety in all distributions of the software, 119522SAndreas.Sandberg@ARM.com# modified or unmodified, in source code or in binary form. 129522SAndreas.Sandberg@ARM.com# 136981SLisa.Hsu@amd.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 146981SLisa.Hsu@amd.com# All rights reserved. 156981SLisa.Hsu@amd.com# 166981SLisa.Hsu@amd.com# Redistribution and use in source and binary forms, with or without 176981SLisa.Hsu@amd.com# modification, are permitted provided that the following conditions are 186981SLisa.Hsu@amd.com# met: redistributions of source code must retain the above copyright 196981SLisa.Hsu@amd.com# notice, this list of conditions and the following disclaimer; 206981SLisa.Hsu@amd.com# redistributions in binary form must reproduce the above copyright 216981SLisa.Hsu@amd.com# notice, this list of conditions and the following disclaimer in the 226981SLisa.Hsu@amd.com# documentation and/or other materials provided with the distribution; 236981SLisa.Hsu@amd.com# neither the name of the copyright holders nor the names of its 246981SLisa.Hsu@amd.com# contributors may be used to endorse or promote products derived from 256981SLisa.Hsu@amd.com# this software without specific prior written permission. 266981SLisa.Hsu@amd.com# 276981SLisa.Hsu@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 286981SLisa.Hsu@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 296981SLisa.Hsu@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 306981SLisa.Hsu@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 316981SLisa.Hsu@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 326981SLisa.Hsu@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 336981SLisa.Hsu@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 346981SLisa.Hsu@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 356981SLisa.Hsu@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 366981SLisa.Hsu@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 376981SLisa.Hsu@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 386981SLisa.Hsu@amd.com# 396981SLisa.Hsu@amd.com# Authors: Lisa Hsu 406981SLisa.Hsu@amd.com 416981SLisa.Hsu@amd.com# Configure the M5 cache hierarchy config in one place 426981SLisa.Hsu@amd.com# 436981SLisa.Hsu@amd.com 446981SLisa.Hsu@amd.comimport m5 456981SLisa.Hsu@amd.comfrom m5.objects import * 466981SLisa.Hsu@amd.comfrom Caches import * 476981SLisa.Hsu@amd.com 486981SLisa.Hsu@amd.comdef config_cache(options, system): 499522SAndreas.Sandberg@ARM.com if options.cpu_type == "arm_detailed": 509522SAndreas.Sandberg@ARM.com try: 519522SAndreas.Sandberg@ARM.com from O3_ARM_v7a import * 529522SAndreas.Sandberg@ARM.com except: 539522SAndreas.Sandberg@ARM.com print "arm_detailed is unavailable. Did you compile the O3 model?" 549522SAndreas.Sandberg@ARM.com sys.exit(1) 559522SAndreas.Sandberg@ARM.com 569522SAndreas.Sandberg@ARM.com dcache_class, icache_class, l2_cache_class = \ 579522SAndreas.Sandberg@ARM.com O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2 589522SAndreas.Sandberg@ARM.com else: 599522SAndreas.Sandberg@ARM.com dcache_class, icache_class, l2_cache_class = \ 609522SAndreas.Sandberg@ARM.com L1Cache, L1Cache, L2Cache 619522SAndreas.Sandberg@ARM.com 629815SAndreas Hansson <andreas.hansson> # Set the cache line size of the system 639815SAndreas Hansson <andreas.hansson> system.cache_line_size = options.cacheline_size 649815SAndreas Hansson <andreas.hansson> 656981SLisa.Hsu@amd.com if options.l2cache: 669284Sandreas.hansson@arm.com # Provide a clock for the L2 and the L1-to-L2 bus here as they 679284Sandreas.hansson@arm.com # are not connected using addTwoLevelCacheHierarchy. Use the 689284Sandreas.hansson@arm.com # same clock as the CPUs, and set the L1-to-L2 bus width to 32 699284Sandreas.hansson@arm.com # bytes (256 bits). 709793Sakash.bagdia@arm.com system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain, 719522SAndreas.Sandberg@ARM.com size=options.l2_size, 729815SAndreas Hansson <andreas.hansson> assoc=options.l2_assoc) 738724Srdreslin@umich.edu 749793Sakash.bagdia@arm.com system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain, 759793Sakash.bagdia@arm.com width = 32) 768839Sandreas.hansson@arm.com system.l2.cpu_side = system.tol2bus.master 778839Sandreas.hansson@arm.com system.l2.mem_side = system.membus.slave 786981SLisa.Hsu@amd.com 796981SLisa.Hsu@amd.com for i in xrange(options.num_cpus): 806981SLisa.Hsu@amd.com if options.caches: 819522SAndreas.Sandberg@ARM.com icache = icache_class(size=options.l1i_size, 829815SAndreas Hansson <andreas.hansson> assoc=options.l1i_assoc) 839522SAndreas.Sandberg@ARM.com dcache = dcache_class(size=options.l1d_size, 849815SAndreas Hansson <andreas.hansson> assoc=options.l1d_assoc) 858724Srdreslin@umich.edu 869284Sandreas.hansson@arm.com # When connecting the caches, the clock is also inherited 879284Sandreas.hansson@arm.com # from the CPU in question 887868Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86': 898056Sksewell@umich.edu system.cpu[i].addPrivateSplitL1Caches(icache, dcache, 907868Sgblack@eecs.umich.edu PageTableWalkerCache(), 917868Sgblack@eecs.umich.edu PageTableWalkerCache()) 927868Sgblack@eecs.umich.edu else: 938056Sksewell@umich.edu system.cpu[i].addPrivateSplitL1Caches(icache, dcache) 948863Snilay@cs.wisc.edu system.cpu[i].createInterruptController() 956981SLisa.Hsu@amd.com if options.l2cache: 967876Sgblack@eecs.umich.edu system.cpu[i].connectAllPorts(system.tol2bus, system.membus) 976981SLisa.Hsu@amd.com else: 987876Sgblack@eecs.umich.edu system.cpu[i].connectAllPorts(system.membus) 996981SLisa.Hsu@amd.com 1006981SLisa.Hsu@amd.com return system 101