CacheConfig.py revision 8839
16981SLisa.Hsu@amd.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 26981SLisa.Hsu@amd.com# All rights reserved. 36981SLisa.Hsu@amd.com# 46981SLisa.Hsu@amd.com# Redistribution and use in source and binary forms, with or without 56981SLisa.Hsu@amd.com# modification, are permitted provided that the following conditions are 66981SLisa.Hsu@amd.com# met: redistributions of source code must retain the above copyright 76981SLisa.Hsu@amd.com# notice, this list of conditions and the following disclaimer; 86981SLisa.Hsu@amd.com# redistributions in binary form must reproduce the above copyright 96981SLisa.Hsu@amd.com# notice, this list of conditions and the following disclaimer in the 106981SLisa.Hsu@amd.com# documentation and/or other materials provided with the distribution; 116981SLisa.Hsu@amd.com# neither the name of the copyright holders nor the names of its 126981SLisa.Hsu@amd.com# contributors may be used to endorse or promote products derived from 136981SLisa.Hsu@amd.com# this software without specific prior written permission. 146981SLisa.Hsu@amd.com# 156981SLisa.Hsu@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166981SLisa.Hsu@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176981SLisa.Hsu@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186981SLisa.Hsu@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196981SLisa.Hsu@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206981SLisa.Hsu@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216981SLisa.Hsu@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226981SLisa.Hsu@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236981SLisa.Hsu@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246981SLisa.Hsu@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256981SLisa.Hsu@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266981SLisa.Hsu@amd.com# 276981SLisa.Hsu@amd.com# Authors: Lisa Hsu 286981SLisa.Hsu@amd.com 296981SLisa.Hsu@amd.com# Configure the M5 cache hierarchy config in one place 306981SLisa.Hsu@amd.com# 316981SLisa.Hsu@amd.com 326981SLisa.Hsu@amd.comimport m5 336981SLisa.Hsu@amd.comfrom m5.objects import * 346981SLisa.Hsu@amd.comfrom Caches import * 358724Srdreslin@umich.edufrom O3_ARM_v7a import * 366981SLisa.Hsu@amd.com 376981SLisa.Hsu@amd.comdef config_cache(options, system): 386981SLisa.Hsu@amd.com if options.l2cache: 398724Srdreslin@umich.edu if options.cpu_type == "arm_detailed": 408724Srdreslin@umich.edu system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc = options.l2_assoc, 418724Srdreslin@umich.edu block_size=options.cacheline_size) 428724Srdreslin@umich.edu else: 438724Srdreslin@umich.edu system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc, 448724Srdreslin@umich.edu block_size=options.cacheline_size) 458724Srdreslin@umich.edu 466981SLisa.Hsu@amd.com system.tol2bus = Bus() 478839Sandreas.hansson@arm.com system.l2.cpu_side = system.tol2bus.master 488839Sandreas.hansson@arm.com system.l2.mem_side = system.membus.slave 496981SLisa.Hsu@amd.com system.l2.num_cpus = options.num_cpus 506981SLisa.Hsu@amd.com 516981SLisa.Hsu@amd.com for i in xrange(options.num_cpus): 526981SLisa.Hsu@amd.com if options.caches: 538724Srdreslin@umich.edu if options.cpu_type == "arm_detailed": 548724Srdreslin@umich.edu icache = O3_ARM_v7a_ICache(size = options.l1i_size, 558724Srdreslin@umich.edu assoc = options.l1i_assoc, 568724Srdreslin@umich.edu block_size=options.cacheline_size) 578724Srdreslin@umich.edu dcache = O3_ARM_v7a_DCache(size = options.l1d_size, 588724Srdreslin@umich.edu assoc = options.l1d_assoc, 598724Srdreslin@umich.edu block_size=options.cacheline_size) 608724Srdreslin@umich.edu else: 618724Srdreslin@umich.edu icache = L1Cache(size = options.l1i_size, 628724Srdreslin@umich.edu assoc = options.l1i_assoc, 638724Srdreslin@umich.edu block_size=options.cacheline_size) 648724Srdreslin@umich.edu dcache = L1Cache(size = options.l1d_size, 658724Srdreslin@umich.edu assoc = options.l1d_assoc, 668724Srdreslin@umich.edu block_size=options.cacheline_size) 678724Srdreslin@umich.edu 687868Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86': 698056Sksewell@umich.edu system.cpu[i].addPrivateSplitL1Caches(icache, dcache, 707868Sgblack@eecs.umich.edu PageTableWalkerCache(), 717868Sgblack@eecs.umich.edu PageTableWalkerCache()) 727868Sgblack@eecs.umich.edu else: 738056Sksewell@umich.edu system.cpu[i].addPrivateSplitL1Caches(icache, dcache) 746981SLisa.Hsu@amd.com if options.l2cache: 757876Sgblack@eecs.umich.edu system.cpu[i].connectAllPorts(system.tol2bus, system.membus) 766981SLisa.Hsu@amd.com else: 777876Sgblack@eecs.umich.edu system.cpu[i].connectAllPorts(system.membus) 786981SLisa.Hsu@amd.com 796981SLisa.Hsu@amd.com return system 80