xref: /gem5/configs/common/CacheConfig.py

# Copyright (c) 2010 Advanced Micro Devices, Inc.
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# Authors: Lisa Hsu

# Configure the M5 cache hierarchy config in one place
#

import m5
from m5.objects import *
from Caches import *

def config_cache(options, system):
    if options.l2cache:
        system.l2 = L2Cache(size='2MB')
        system.tol2bus = Bus()
        system.l2.cpu_side = system.tol2bus.port
        system.l2.mem_side = system.membus.port
        system.l2.num_cpus = options.num_cpus

    for i in xrange(options.num_cpus):
        if options.caches:
            if buildEnv['TARGET_ISA'] == 'x86':
                system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
                                                      L1Cache(size = '64kB'),
                                                      PageTableWalkerCache(),
                                                      PageTableWalkerCache())
            else:
                system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
                                                      L1Cache(size = '64kB'))
        if options.l2cache:
            system.cpu[i].connectMemPorts(system.tol2bus)
        else:
            system.cpu[i].connectMemPorts(system.membus)

    return system