CacheConfig.py revision 12097
111539Sandreas.hansson@arm.com# Copyright (c) 2012-2013, 2015-2016 ARM Limited 29522SAndreas.Sandberg@ARM.com# All rights reserved 311320Ssteve.reinhardt@amd.com# 49522SAndreas.Sandberg@ARM.com# The license below extends only to copyright in the software and shall 59522SAndreas.Sandberg@ARM.com# not be construed as granting a license to any other intellectual 69522SAndreas.Sandberg@ARM.com# property including but not limited to intellectual property relating 79522SAndreas.Sandberg@ARM.com# to a hardware implementation of the functionality of the software 89522SAndreas.Sandberg@ARM.com# licensed hereunder. You may use the software subject to the license 99522SAndreas.Sandberg@ARM.com# terms below provided that you ensure that this notice is replicated 109522SAndreas.Sandberg@ARM.com# unmodified and in its entirety in all distributions of the software, 119522SAndreas.Sandberg@ARM.com# modified or unmodified, in source code or in binary form. 1211320Ssteve.reinhardt@amd.com# 136981SLisa.Hsu@amd.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 146981SLisa.Hsu@amd.com# All rights reserved. 156981SLisa.Hsu@amd.com# 166981SLisa.Hsu@amd.com# Redistribution and use in source and binary forms, with or without 176981SLisa.Hsu@amd.com# modification, are permitted provided that the following conditions are 186981SLisa.Hsu@amd.com# met: redistributions of source code must retain the above copyright 196981SLisa.Hsu@amd.com# notice, this list of conditions and the following disclaimer; 206981SLisa.Hsu@amd.com# redistributions in binary form must reproduce the above copyright 216981SLisa.Hsu@amd.com# notice, this list of conditions and the following disclaimer in the 226981SLisa.Hsu@amd.com# documentation and/or other materials provided with the distribution; 236981SLisa.Hsu@amd.com# neither the name of the copyright holders nor the names of its 246981SLisa.Hsu@amd.com# contributors may be used to endorse or promote products derived from 256981SLisa.Hsu@amd.com# this software without specific prior written permission. 266981SLisa.Hsu@amd.com# 276981SLisa.Hsu@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 286981SLisa.Hsu@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 296981SLisa.Hsu@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 306981SLisa.Hsu@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 316981SLisa.Hsu@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 326981SLisa.Hsu@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 336981SLisa.Hsu@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 346981SLisa.Hsu@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 356981SLisa.Hsu@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 366981SLisa.Hsu@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 376981SLisa.Hsu@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 386981SLisa.Hsu@amd.com# 396981SLisa.Hsu@amd.com# Authors: Lisa Hsu 406981SLisa.Hsu@amd.com 416981SLisa.Hsu@amd.com# Configure the M5 cache hierarchy config in one place 426981SLisa.Hsu@amd.com# 436981SLisa.Hsu@amd.com 446981SLisa.Hsu@amd.comimport m5 456981SLisa.Hsu@amd.comfrom m5.objects import * 466981SLisa.Hsu@amd.comfrom Caches import * 476981SLisa.Hsu@amd.com 486981SLisa.Hsu@amd.comdef config_cache(options, system): 4910780SCurtis.Dunham@arm.com if options.external_memory_system and (options.caches or options.l2cache): 5010780SCurtis.Dunham@arm.com print "External caches and internal caches are exclusive options.\n" 5110780SCurtis.Dunham@arm.com sys.exit(1) 5210780SCurtis.Dunham@arm.com 5310780SCurtis.Dunham@arm.com if options.external_memory_system: 5410780SCurtis.Dunham@arm.com ExternalCache = ExternalCacheFactory(options.external_memory_system) 5510780SCurtis.Dunham@arm.com 5612014Sgabeblack@google.com if options.cpu_type == "O3_ARM_v7a_3": 579522SAndreas.Sandberg@ARM.com try: 5812097Sandreas.sandberg@arm.com from cores.arm.O3_ARM_v7a import * 599522SAndreas.Sandberg@ARM.com except: 6012097Sandreas.sandberg@arm.com print "O3_ARM_v7a_3 is unavailable. Did you compile the O3 model?" 619522SAndreas.Sandberg@ARM.com sys.exit(1) 629522SAndreas.Sandberg@ARM.com 6311539Sandreas.hansson@arm.com dcache_class, icache_class, l2_cache_class, walk_cache_class = \ 6411539Sandreas.hansson@arm.com O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, \ 6511539Sandreas.hansson@arm.com O3_ARM_v7aWalkCache 669522SAndreas.Sandberg@ARM.com else: 6711539Sandreas.hansson@arm.com dcache_class, icache_class, l2_cache_class, walk_cache_class = \ 6811539Sandreas.hansson@arm.com L1_DCache, L1_ICache, L2Cache, None 6911539Sandreas.hansson@arm.com 7011539Sandreas.hansson@arm.com if buildEnv['TARGET_ISA'] == 'x86': 7111539Sandreas.hansson@arm.com walk_cache_class = PageTableWalkerCache 729522SAndreas.Sandberg@ARM.com 739815SAndreas Hansson <andreas.hansson> # Set the cache line size of the system 749815SAndreas Hansson <andreas.hansson> system.cache_line_size = options.cacheline_size 759815SAndreas Hansson <andreas.hansson> 7611251Sradhika.jagtap@ARM.com # If elastic trace generation is enabled, make sure the memory system is 7711251Sradhika.jagtap@ARM.com # minimal so that compute delays do not include memory access latencies. 7811251Sradhika.jagtap@ARM.com # Configure the compulsory L1 caches for the O3CPU, do not configure 7911251Sradhika.jagtap@ARM.com # any more caches. 8011251Sradhika.jagtap@ARM.com if options.l2cache and options.elastic_trace_en: 8111251Sradhika.jagtap@ARM.com fatal("When elastic trace is enabled, do not configure L2 caches.") 8211251Sradhika.jagtap@ARM.com 836981SLisa.Hsu@amd.com if options.l2cache: 849284Sandreas.hansson@arm.com # Provide a clock for the L2 and the L1-to-L2 bus here as they 859284Sandreas.hansson@arm.com # are not connected using addTwoLevelCacheHierarchy. Use the 8610720Sandreas.hansson@arm.com # same clock as the CPUs. 879793Sakash.bagdia@arm.com system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain, 889522SAndreas.Sandberg@ARM.com size=options.l2_size, 899815SAndreas Hansson <andreas.hansson> assoc=options.l2_assoc) 908724Srdreslin@umich.edu 9110720Sandreas.hansson@arm.com system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain) 928839Sandreas.hansson@arm.com system.l2.cpu_side = system.tol2bus.master 938839Sandreas.hansson@arm.com system.l2.mem_side = system.membus.slave 946981SLisa.Hsu@amd.com 9510613SMarco.Elver@ARM.com if options.memchecker: 9610613SMarco.Elver@ARM.com system.memchecker = MemChecker() 9710613SMarco.Elver@ARM.com 986981SLisa.Hsu@amd.com for i in xrange(options.num_cpus): 996981SLisa.Hsu@amd.com if options.caches: 1009522SAndreas.Sandberg@ARM.com icache = icache_class(size=options.l1i_size, 1019815SAndreas Hansson <andreas.hansson> assoc=options.l1i_assoc) 1029522SAndreas.Sandberg@ARM.com dcache = dcache_class(size=options.l1d_size, 1039815SAndreas Hansson <andreas.hansson> assoc=options.l1d_assoc) 1048724Srdreslin@umich.edu 10511539Sandreas.hansson@arm.com # If we have a walker cache specified, instantiate two 10611539Sandreas.hansson@arm.com # instances here 10711539Sandreas.hansson@arm.com if walk_cache_class: 10811539Sandreas.hansson@arm.com iwalkcache = walk_cache_class() 10911539Sandreas.hansson@arm.com dwalkcache = walk_cache_class() 11011539Sandreas.hansson@arm.com else: 11111539Sandreas.hansson@arm.com iwalkcache = None 11211539Sandreas.hansson@arm.com dwalkcache = None 11311539Sandreas.hansson@arm.com 11410613SMarco.Elver@ARM.com if options.memchecker: 11510613SMarco.Elver@ARM.com dcache_mon = MemCheckerMonitor(warn_only=True) 11610613SMarco.Elver@ARM.com dcache_real = dcache 11710613SMarco.Elver@ARM.com 11810613SMarco.Elver@ARM.com # Do not pass the memchecker into the constructor of 11910613SMarco.Elver@ARM.com # MemCheckerMonitor, as it would create a copy; we require 12010613SMarco.Elver@ARM.com # exactly one MemChecker instance. 12110613SMarco.Elver@ARM.com dcache_mon.memchecker = system.memchecker 12210613SMarco.Elver@ARM.com 12310613SMarco.Elver@ARM.com # Connect monitor 12410613SMarco.Elver@ARM.com dcache_mon.mem_side = dcache.cpu_side 12510613SMarco.Elver@ARM.com 12610613SMarco.Elver@ARM.com # Let CPU connect to monitors 12710613SMarco.Elver@ARM.com dcache = dcache_mon 12810613SMarco.Elver@ARM.com 1299284Sandreas.hansson@arm.com # When connecting the caches, the clock is also inherited 1309284Sandreas.hansson@arm.com # from the CPU in question 13111539Sandreas.hansson@arm.com system.cpu[i].addPrivateSplitL1Caches(icache, dcache, 13211539Sandreas.hansson@arm.com iwalkcache, dwalkcache) 13310613SMarco.Elver@ARM.com 13410613SMarco.Elver@ARM.com if options.memchecker: 13510613SMarco.Elver@ARM.com # The mem_side ports of the caches haven't been connected yet. 13610613SMarco.Elver@ARM.com # Make sure connectAllPorts connects the right objects. 13710613SMarco.Elver@ARM.com system.cpu[i].dcache = dcache_real 13810613SMarco.Elver@ARM.com system.cpu[i].dcache_mon = dcache_mon 13910613SMarco.Elver@ARM.com 14010780SCurtis.Dunham@arm.com elif options.external_memory_system: 14110780SCurtis.Dunham@arm.com # These port names are presented to whatever 'external' system 14210780SCurtis.Dunham@arm.com # gem5 is connecting to. Its configuration will likely depend 14310780SCurtis.Dunham@arm.com # on these names. For simplicity, we would advise configuring 14410780SCurtis.Dunham@arm.com # it to use this naming scheme; if this isn't possible, change 14510780SCurtis.Dunham@arm.com # the names below. 14610780SCurtis.Dunham@arm.com if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 14710780SCurtis.Dunham@arm.com system.cpu[i].addPrivateSplitL1Caches( 14810780SCurtis.Dunham@arm.com ExternalCache("cpu%d.icache" % i), 14910780SCurtis.Dunham@arm.com ExternalCache("cpu%d.dcache" % i), 15010780SCurtis.Dunham@arm.com ExternalCache("cpu%d.itb_walker_cache" % i), 15110780SCurtis.Dunham@arm.com ExternalCache("cpu%d.dtb_walker_cache" % i)) 15210780SCurtis.Dunham@arm.com else: 15310780SCurtis.Dunham@arm.com system.cpu[i].addPrivateSplitL1Caches( 15410780SCurtis.Dunham@arm.com ExternalCache("cpu%d.icache" % i), 15510780SCurtis.Dunham@arm.com ExternalCache("cpu%d.dcache" % i)) 15610780SCurtis.Dunham@arm.com 1578863Snilay@cs.wisc.edu system.cpu[i].createInterruptController() 1586981SLisa.Hsu@amd.com if options.l2cache: 1597876Sgblack@eecs.umich.edu system.cpu[i].connectAllPorts(system.tol2bus, system.membus) 16010780SCurtis.Dunham@arm.com elif options.external_memory_system: 16110780SCurtis.Dunham@arm.com system.cpu[i].connectUncachedPorts(system.membus) 1626981SLisa.Hsu@amd.com else: 1637876Sgblack@eecs.umich.edu system.cpu[i].connectAllPorts(system.membus) 1646981SLisa.Hsu@amd.com 1656981SLisa.Hsu@amd.com return system 16610780SCurtis.Dunham@arm.com 16710780SCurtis.Dunham@arm.com# ExternalSlave provides a "port", but when that port connects to a cache, 16810780SCurtis.Dunham@arm.com# the connecting CPU SimObject wants to refer to its "cpu_side". 16910780SCurtis.Dunham@arm.com# The 'ExternalCache' class provides this adaptation by rewriting the name, 17010780SCurtis.Dunham@arm.com# eliminating distracting changes elsewhere in the config code. 17110780SCurtis.Dunham@arm.comclass ExternalCache(ExternalSlave): 17210780SCurtis.Dunham@arm.com def __getattr__(cls, attr): 17310780SCurtis.Dunham@arm.com if (attr == "cpu_side"): 17410780SCurtis.Dunham@arm.com attr = "port" 17510780SCurtis.Dunham@arm.com return super(ExternalSlave, cls).__getattr__(attr) 17610780SCurtis.Dunham@arm.com 17710780SCurtis.Dunham@arm.com def __setattr__(cls, attr, value): 17810780SCurtis.Dunham@arm.com if (attr == "cpu_side"): 17910780SCurtis.Dunham@arm.com attr = "port" 18010780SCurtis.Dunham@arm.com return super(ExternalSlave, cls).__setattr__(attr, value) 18110780SCurtis.Dunham@arm.com 18210780SCurtis.Dunham@arm.comdef ExternalCacheFactory(port_type): 18310780SCurtis.Dunham@arm.com def make(name): 18410780SCurtis.Dunham@arm.com return ExternalCache(port_data=name, port_type=port_type, 18510780SCurtis.Dunham@arm.com addr_ranges=[AllMemory]) 18610780SCurtis.Dunham@arm.com return make 187