CacheConfig.py revision 11501
110780SCurtis.Dunham@arm.com# Copyright (c) 2012-2013, 2015 ARM Limited 29522SAndreas.Sandberg@ARM.com# All rights reserved 311320Ssteve.reinhardt@amd.com# 49522SAndreas.Sandberg@ARM.com# The license below extends only to copyright in the software and shall 59522SAndreas.Sandberg@ARM.com# not be construed as granting a license to any other intellectual 69522SAndreas.Sandberg@ARM.com# property including but not limited to intellectual property relating 79522SAndreas.Sandberg@ARM.com# to a hardware implementation of the functionality of the software 89522SAndreas.Sandberg@ARM.com# licensed hereunder. You may use the software subject to the license 99522SAndreas.Sandberg@ARM.com# terms below provided that you ensure that this notice is replicated 109522SAndreas.Sandberg@ARM.com# unmodified and in its entirety in all distributions of the software, 119522SAndreas.Sandberg@ARM.com# modified or unmodified, in source code or in binary form. 1211320Ssteve.reinhardt@amd.com# 136981SLisa.Hsu@amd.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 146981SLisa.Hsu@amd.com# All rights reserved. 156981SLisa.Hsu@amd.com# 166981SLisa.Hsu@amd.com# Redistribution and use in source and binary forms, with or without 176981SLisa.Hsu@amd.com# modification, are permitted provided that the following conditions are 186981SLisa.Hsu@amd.com# met: redistributions of source code must retain the above copyright 196981SLisa.Hsu@amd.com# notice, this list of conditions and the following disclaimer; 206981SLisa.Hsu@amd.com# redistributions in binary form must reproduce the above copyright 216981SLisa.Hsu@amd.com# notice, this list of conditions and the following disclaimer in the 226981SLisa.Hsu@amd.com# documentation and/or other materials provided with the distribution; 236981SLisa.Hsu@amd.com# neither the name of the copyright holders nor the names of its 246981SLisa.Hsu@amd.com# contributors may be used to endorse or promote products derived from 256981SLisa.Hsu@amd.com# this software without specific prior written permission. 266981SLisa.Hsu@amd.com# 276981SLisa.Hsu@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 286981SLisa.Hsu@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 296981SLisa.Hsu@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 306981SLisa.Hsu@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 316981SLisa.Hsu@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 326981SLisa.Hsu@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 336981SLisa.Hsu@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 346981SLisa.Hsu@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 356981SLisa.Hsu@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 366981SLisa.Hsu@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 376981SLisa.Hsu@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 386981SLisa.Hsu@amd.com# 396981SLisa.Hsu@amd.com# Authors: Lisa Hsu 406981SLisa.Hsu@amd.com 416981SLisa.Hsu@amd.com# Configure the M5 cache hierarchy config in one place 426981SLisa.Hsu@amd.com# 436981SLisa.Hsu@amd.com 446981SLisa.Hsu@amd.comimport m5 456981SLisa.Hsu@amd.comfrom m5.objects import * 466981SLisa.Hsu@amd.comfrom Caches import * 476981SLisa.Hsu@amd.com 486981SLisa.Hsu@amd.comdef config_cache(options, system): 4910780SCurtis.Dunham@arm.com if options.external_memory_system and (options.caches or options.l2cache): 5010780SCurtis.Dunham@arm.com print "External caches and internal caches are exclusive options.\n" 5110780SCurtis.Dunham@arm.com sys.exit(1) 5210780SCurtis.Dunham@arm.com 5310780SCurtis.Dunham@arm.com if options.external_memory_system: 5410780SCurtis.Dunham@arm.com ExternalCache = ExternalCacheFactory(options.external_memory_system) 5510780SCurtis.Dunham@arm.com 569522SAndreas.Sandberg@ARM.com if options.cpu_type == "arm_detailed": 579522SAndreas.Sandberg@ARM.com try: 589522SAndreas.Sandberg@ARM.com from O3_ARM_v7a import * 599522SAndreas.Sandberg@ARM.com except: 609522SAndreas.Sandberg@ARM.com print "arm_detailed is unavailable. Did you compile the O3 model?" 619522SAndreas.Sandberg@ARM.com sys.exit(1) 629522SAndreas.Sandberg@ARM.com 639522SAndreas.Sandberg@ARM.com dcache_class, icache_class, l2_cache_class = \ 649522SAndreas.Sandberg@ARM.com O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2 659522SAndreas.Sandberg@ARM.com else: 669522SAndreas.Sandberg@ARM.com dcache_class, icache_class, l2_cache_class = \ 6710884Sandreas.hansson@arm.com L1_DCache, L1_ICache, L2Cache 689522SAndreas.Sandberg@ARM.com 699815SAndreas Hansson <andreas.hansson> # Set the cache line size of the system 709815SAndreas Hansson <andreas.hansson> system.cache_line_size = options.cacheline_size 719815SAndreas Hansson <andreas.hansson> 7211251Sradhika.jagtap@ARM.com # If elastic trace generation is enabled, make sure the memory system is 7311251Sradhika.jagtap@ARM.com # minimal so that compute delays do not include memory access latencies. 7411251Sradhika.jagtap@ARM.com # Configure the compulsory L1 caches for the O3CPU, do not configure 7511251Sradhika.jagtap@ARM.com # any more caches. 7611251Sradhika.jagtap@ARM.com if options.l2cache and options.elastic_trace_en: 7711251Sradhika.jagtap@ARM.com fatal("When elastic trace is enabled, do not configure L2 caches.") 7811251Sradhika.jagtap@ARM.com 796981SLisa.Hsu@amd.com if options.l2cache: 809284Sandreas.hansson@arm.com # Provide a clock for the L2 and the L1-to-L2 bus here as they 819284Sandreas.hansson@arm.com # are not connected using addTwoLevelCacheHierarchy. Use the 8210720Sandreas.hansson@arm.com # same clock as the CPUs. 839793Sakash.bagdia@arm.com system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain, 849522SAndreas.Sandberg@ARM.com size=options.l2_size, 859815SAndreas Hansson <andreas.hansson> assoc=options.l2_assoc) 868724Srdreslin@umich.edu 8710720Sandreas.hansson@arm.com system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain) 888839Sandreas.hansson@arm.com system.l2.cpu_side = system.tol2bus.master 898839Sandreas.hansson@arm.com system.l2.mem_side = system.membus.slave 906981SLisa.Hsu@amd.com 9110613SMarco.Elver@ARM.com if options.memchecker: 9210613SMarco.Elver@ARM.com system.memchecker = MemChecker() 9310613SMarco.Elver@ARM.com 946981SLisa.Hsu@amd.com for i in xrange(options.num_cpus): 956981SLisa.Hsu@amd.com if options.caches: 969522SAndreas.Sandberg@ARM.com icache = icache_class(size=options.l1i_size, 979815SAndreas Hansson <andreas.hansson> assoc=options.l1i_assoc) 989522SAndreas.Sandberg@ARM.com dcache = dcache_class(size=options.l1d_size, 999815SAndreas Hansson <andreas.hansson> assoc=options.l1d_assoc) 1008724Srdreslin@umich.edu 10110613SMarco.Elver@ARM.com if options.memchecker: 10210613SMarco.Elver@ARM.com dcache_mon = MemCheckerMonitor(warn_only=True) 10310613SMarco.Elver@ARM.com dcache_real = dcache 10410613SMarco.Elver@ARM.com 10510613SMarco.Elver@ARM.com # Do not pass the memchecker into the constructor of 10610613SMarco.Elver@ARM.com # MemCheckerMonitor, as it would create a copy; we require 10710613SMarco.Elver@ARM.com # exactly one MemChecker instance. 10810613SMarco.Elver@ARM.com dcache_mon.memchecker = system.memchecker 10910613SMarco.Elver@ARM.com 11010613SMarco.Elver@ARM.com # Connect monitor 11110613SMarco.Elver@ARM.com dcache_mon.mem_side = dcache.cpu_side 11210613SMarco.Elver@ARM.com 11310613SMarco.Elver@ARM.com # Let CPU connect to monitors 11410613SMarco.Elver@ARM.com dcache = dcache_mon 11510613SMarco.Elver@ARM.com 1169284Sandreas.hansson@arm.com # When connecting the caches, the clock is also inherited 1179284Sandreas.hansson@arm.com # from the CPU in question 1187868Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86': 1198056Sksewell@umich.edu system.cpu[i].addPrivateSplitL1Caches(icache, dcache, 1207868Sgblack@eecs.umich.edu PageTableWalkerCache(), 1217868Sgblack@eecs.umich.edu PageTableWalkerCache()) 1227868Sgblack@eecs.umich.edu else: 1238056Sksewell@umich.edu system.cpu[i].addPrivateSplitL1Caches(icache, dcache) 12410613SMarco.Elver@ARM.com 12510613SMarco.Elver@ARM.com if options.memchecker: 12610613SMarco.Elver@ARM.com # The mem_side ports of the caches haven't been connected yet. 12710613SMarco.Elver@ARM.com # Make sure connectAllPorts connects the right objects. 12810613SMarco.Elver@ARM.com system.cpu[i].dcache = dcache_real 12910613SMarco.Elver@ARM.com system.cpu[i].dcache_mon = dcache_mon 13010613SMarco.Elver@ARM.com 13110780SCurtis.Dunham@arm.com elif options.external_memory_system: 13210780SCurtis.Dunham@arm.com # These port names are presented to whatever 'external' system 13310780SCurtis.Dunham@arm.com # gem5 is connecting to. Its configuration will likely depend 13410780SCurtis.Dunham@arm.com # on these names. For simplicity, we would advise configuring 13510780SCurtis.Dunham@arm.com # it to use this naming scheme; if this isn't possible, change 13610780SCurtis.Dunham@arm.com # the names below. 13710780SCurtis.Dunham@arm.com if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 13810780SCurtis.Dunham@arm.com system.cpu[i].addPrivateSplitL1Caches( 13910780SCurtis.Dunham@arm.com ExternalCache("cpu%d.icache" % i), 14010780SCurtis.Dunham@arm.com ExternalCache("cpu%d.dcache" % i), 14110780SCurtis.Dunham@arm.com ExternalCache("cpu%d.itb_walker_cache" % i), 14210780SCurtis.Dunham@arm.com ExternalCache("cpu%d.dtb_walker_cache" % i)) 14310780SCurtis.Dunham@arm.com else: 14410780SCurtis.Dunham@arm.com system.cpu[i].addPrivateSplitL1Caches( 14510780SCurtis.Dunham@arm.com ExternalCache("cpu%d.icache" % i), 14610780SCurtis.Dunham@arm.com ExternalCache("cpu%d.dcache" % i)) 14710780SCurtis.Dunham@arm.com 1488863Snilay@cs.wisc.edu system.cpu[i].createInterruptController() 1496981SLisa.Hsu@amd.com if options.l2cache: 1507876Sgblack@eecs.umich.edu system.cpu[i].connectAllPorts(system.tol2bus, system.membus) 15110780SCurtis.Dunham@arm.com elif options.external_memory_system: 15210780SCurtis.Dunham@arm.com system.cpu[i].connectUncachedPorts(system.membus) 1536981SLisa.Hsu@amd.com else: 1547876Sgblack@eecs.umich.edu system.cpu[i].connectAllPorts(system.membus) 1556981SLisa.Hsu@amd.com 15611501Sstephan.diestelhorst@arm.com # Add a snoop filter to the membus if there are caches above it 15711501Sstephan.diestelhorst@arm.com if (options.l2cache or options.caches) and \ 15811501Sstephan.diestelhorst@arm.com (system.membus.snoop_filter == NULL): 15911501Sstephan.diestelhorst@arm.com system.membus.snoop_filter = SnoopFilter() 16011501Sstephan.diestelhorst@arm.com 1616981SLisa.Hsu@amd.com return system 16210780SCurtis.Dunham@arm.com 16310780SCurtis.Dunham@arm.com# ExternalSlave provides a "port", but when that port connects to a cache, 16410780SCurtis.Dunham@arm.com# the connecting CPU SimObject wants to refer to its "cpu_side". 16510780SCurtis.Dunham@arm.com# The 'ExternalCache' class provides this adaptation by rewriting the name, 16610780SCurtis.Dunham@arm.com# eliminating distracting changes elsewhere in the config code. 16710780SCurtis.Dunham@arm.comclass ExternalCache(ExternalSlave): 16810780SCurtis.Dunham@arm.com def __getattr__(cls, attr): 16910780SCurtis.Dunham@arm.com if (attr == "cpu_side"): 17010780SCurtis.Dunham@arm.com attr = "port" 17110780SCurtis.Dunham@arm.com return super(ExternalSlave, cls).__getattr__(attr) 17210780SCurtis.Dunham@arm.com 17310780SCurtis.Dunham@arm.com def __setattr__(cls, attr, value): 17410780SCurtis.Dunham@arm.com if (attr == "cpu_side"): 17510780SCurtis.Dunham@arm.com attr = "port" 17610780SCurtis.Dunham@arm.com return super(ExternalSlave, cls).__setattr__(attr, value) 17710780SCurtis.Dunham@arm.com 17810780SCurtis.Dunham@arm.comdef ExternalCacheFactory(port_type): 17910780SCurtis.Dunham@arm.com def make(name): 18010780SCurtis.Dunham@arm.com return ExternalCache(port_data=name, port_type=port_type, 18110780SCurtis.Dunham@arm.com addr_ranges=[AllMemory]) 18210780SCurtis.Dunham@arm.com return make 183