Searched refs:tBURST (Results 1 - 6 of 6) sorted by relevance
/gem5/src/mem/ |
H A D | DRAMCtrl.py | 181 # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 182 # With bank group architectures, tBURST represents the CAS-to-CAS 184 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") variable in class:DRAMCtrl 188 # tBURST is equivalent to tCCD_S; no explicit parameter required 357 tBURST = '5ns' variable in class:DDR3_1600_8x8 455 tBURST = '3.2ns' variable in class:HMC_2500_1x32 513 tBURST = '3.752ns' variable in class:DDR3_2133_8x8 577 # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 578 # With bank group architectures, tBURST represents the CAS-to-CAS 580 tBURST variable in class:DDR4_2400_16x4 768 tBURST = '7.5ns' variable in class:LPDDR2_S4_1066_1x32 860 tBURST = '20ns' variable in class:WideIO_200_1x128 936 tBURST = '5ns' variable in class:LPDDR3_1600_1x32 1023 tBURST = '2ns' variable in class:GDDR5_4000_2x32 1121 tBURST = '4ns' variable in class:HBM_1000_4H_1x128 [all...] |
H A D | dram_ctrl.cc | 86 tCK(p->tCK), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST), 91 activationLimit(p->activation_limit), rankToRankDly(tCS + tBURST), 92 wrToRdDly(tCL + tBURST + p->tWTR), rdToWrDly(tRTW + tBURST), 166 if (tCCD_L <= tBURST) { 167 fatal("tCCD_L (%d) should be larger than tBURST (%d) when " 169 tCCD_L, tBURST, bankGroupsPerRank); 172 if (tCCD_L_WR <= tBURST) { 173 fatal("tCCD_L_WR (%d) should be larger than tBURST ( [all...] |
H A D | drampower.cc | 155 uint32_t burst_cycles = divCeil(p->tBURST, p->tCK);
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H A D | dram_ctrl.hh | 990 const Tick tBURST; member in class:DRAMCtrl
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/gem5/configs/dram/ |
H A D | sweep.py | 155 itt = system.mem_ctrls[0].tBURST.value * 1000000000000
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H A D | low_power_sweep.py | 157 itt_min = system.mem_ctrls[0].tBURST.value * 1000000000000
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