Lines Matching refs:tBURST
86 tCK(p->tCK), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST),
91 activationLimit(p->activation_limit), rankToRankDly(tCS + tBURST),
92 wrToRdDly(tCL + tBURST + p->tWTR), rdToWrDly(tRTW + tBURST),
166 if (tCCD_L <= tBURST) {
167 fatal("tCCD_L (%d) should be larger than tBURST (%d) when "
169 tCCD_L, tBURST, bankGroupsPerRank);
172 if (tCCD_L_WR <= tBURST) {
173 fatal("tCCD_L_WR (%d) should be larger than tBURST (%d) when "
175 tCCD_L_WR, tBURST, bankGroupsPerRank);
1150 // the command; need minimum of tBURST between commands
1154 dram_pkt->readyTime = cmd_at + tCL + tBURST;
1164 // tBURST; Add tCS for different ranks
1178 // tBURST is default requirement for diff BG timing
1180 dly_to_rd_cmd = dram_pkt->isRead() ? tBURST : wrToRdDly;
1181 dly_to_wr_cmd = dram_pkt->isRead() ? rdToWrDly : tBURST;
1276 nextBurstAt = cmd_at + tBURST;
1316 totBusLat += tBURST;
2718 peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000;