/gem5/tests/test-progs/insttest/src/riscv/ |
H A D | rv64m.h | 41 mul(int64_t rs1, int64_t rs2) argument 44 ROP("mul", rd, rs1, rs2); 49 mulh(int64_t rs1, int64_t rs2) argument 52 ROP("mulh", rd, rs1, rs2); 57 mulhsu(int64_t rs1, uint64_t rs2) argument 60 ROP("mulhsu", rd, rs1, rs2); 65 mulhu(uint64_t rs1, uint64_t rs2) argument 68 ROP("mulhu", rd, rs1, rs2); 73 div(int64_t rs1, int64_t rs2) argument 76 ROP("div", rd, rs1, rs 81 divu(uint64_t rs1, uint64_t rs2) argument 89 rem(int64_t rs1, int64_t rs2) argument 97 remu(uint64_t rs1, uint64_t rs2) argument 105 mulw(int64_t rs1, int64_t rs2) argument 113 divw(int64_t rs1, int64_t rs2) argument 121 divuw(uint64_t rs1, uint64_t rs2) argument 129 remw(int64_t rs1, int64_t rs2) argument 137 remuw(uint64_t rs1, uint64_t rs2) argument [all...] |
H A D | rv64i.h | 217 addi(int64_t rs1, const int16_t imm) argument 220 IOP("addi", rd, rs1, imm); 225 slti(int64_t rs1, const int16_t imm) argument 228 IOP("slti", rd, rs1, imm); 233 sltiu(uint64_t rs1, const uint16_t imm) argument 236 IOP("sltiu", rd, rs1, imm); 241 xori(uint64_t rs1, const uint16_t imm) argument 244 IOP("xori", rd, rs1, imm); 249 ori(uint64_t rs1, const uint16_t imm) argument 252 IOP("ori", rd, rs1, im 257 andi(uint64_t rs1, const uint16_t imm) argument 265 slli(int64_t rs1, const uint16_t imm) argument 273 srli(uint64_t rs1, const uint16_t imm) argument 281 srai(int64_t rs1, const uint16_t imm) argument 289 add(int64_t rs1, int64_t rs2) argument 297 sub(int64_t rs1, int64_t rs2) argument 305 sll(int64_t rs1, int64_t rs2) argument 313 slt(int64_t rs1, int64_t rs2) argument 321 sltu(uint64_t rs1, uint64_t rs2) argument 329 xor_inst(uint64_t rs1, uint64_t rs2) argument 337 srl(uint64_t rs1, uint64_t rs2) argument 345 sra(int64_t rs1, int64_t rs2) argument 353 or_inst(uint64_t rs1, uint64_t rs2) argument 361 and_inst(uint64_t rs1, uint64_t rs2) argument 369 addiw(int64_t rs1, const int16_t imm) argument 377 slliw(int64_t rs1, const uint16_t imm) argument 385 srliw(uint64_t rs1, const uint16_t imm) argument 393 sraiw(int64_t rs1, const uint16_t imm) argument 401 addw(int64_t rs1, int64_t rs2) argument 409 subw(int64_t rs1, int64_t rs2) argument 417 sllw(int64_t rs1, int64_t rs2) argument 425 srlw(uint64_t rs1, uint64_t rs2) argument 433 sraw(int64_t rs1, int64_t rs2) argument [all...] |
H A D | rv64f.h | 92 fsflags(uint64_t rs1) argument 95 asm volatile("fsflags %0,%1" : "=r" (rd) : "r" (rs1)); 269 fcvt_s_w(int64_t rs1) argument 272 asm volatile("fcvt.s.w %0,%1" : "=f" (fd) : "r" (rs1)); 277 fcvt_s_wu(uint64_t rs1) argument 280 asm volatile("fcvt.s.wu %0,%1" : "=f" (fd) : "r" (rs1)); 285 fmv_s_x(uint64_t rs1) argument 288 asm volatile("fmv.s.x %0,%1" : "=f" (fd) : "r" (rs1)); 309 fscsr(uint64_t rs1) argument 312 asm volatile("fscsr %0,%1" : "=r" (rd) : "r" (rs1)); 317 fsrm(uint64_t rs1) argument 342 fcvt_s_l(int64_t rs1) argument 350 fcvt_s_lu(uint64_t rs1) argument [all...] |
H A D | insttest.h | 39 #define IOP(inst, rd, rs1, imm) \ 40 asm volatile(inst " %0,%1,%2" : "=r" (rd) : "r" (rs1), "i" (imm)) 42 #define ROP(inst, rd, rs1, rs2) \ 43 asm volatile(inst " %0,%1,%2" : "=r" (rd) : "r" (rs1), "r" (rs2))
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H A D | rv64d.h | 260 fcvt_d_w(int64_t rs1) argument 263 asm volatile("fcvt.d.w %0,%1" : "=f" (fd) : "r" (rs1)); 268 fcvt_d_wu(uint64_t rs1) argument 271 asm volatile("fcvt.d.wu %0,%1" : "=f" (fd) : "r" (rs1)); 300 fcvt_d_l(int64_t rs1) argument 303 asm volatile("fcvt.d.l %0,%1" : "=f" (fd) : "r" (rs1)); 308 fcvt_d_lu(uint64_t rs1) argument 311 asm volatile("fcvt.d.lu %0,%1" : "=f" (fd) : "r" (rs1)); 316 fmv_d_x(uint64_t rs1) argument 319 asm volatile("fmv.d.x %0,%1" : "=f" (fd) : "r" (rs1)); [all...] |
/gem5/util/m5/ |
H A D | m5op_sparc.S | 37 #define INST(func, rs1, rs2, rd) \ 39 (rs1) << 14 | (rs2) << 0;
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ud/ |
H A D | move.S | 42 #define TEST_FSGNJS(n, rd, rs1, rs2) \ 44 li a1, rs1; \ 51 li a1, rs1; \ 74 #define TEST_FSGNJD_SP(n, isnan, rd, rs1, rs2) \ 76 li a1, rs1; \ 87 li a1, rs1; \
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64mi/ |
H A D | access.S | 24 # after the pc is set to rs1, an access exception should be raised.
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