Searched refs:post (Results 1 - 25 of 29) sorted by relevance

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/gem5/src/cpu/
H A Dintr_control.hh50 void post(int cpu_id, int int_num, int index);
59 post(int int_num, int index = 0) function in class:IntrControl
61 post(0, int_num, index);
H A Dintr_control_noisa.cc41 IntrControl::post(int cpu_id, int int_num, int index) function in class:IntrControl
H A Dintr_control.cc50 IntrControl::post(int cpu_id, int int_num, int index) function in class:IntrControl
52 DPRINTF(IntrControl, "post %d:%d (cpu %d)\n", int_num, index, cpu_id);
H A Dbase.hh240 interrupts[tid]->post(int_num, index);
/gem5/src/systemc/ext/channel/
H A Dsc_semaphore_if.hh43 virtual int post() = 0;
H A Dsc_semaphore.hh48 virtual int post();
/gem5/src/systemc/tests/systemc/communication/sc_semaphore/test01/
H A Dtest01.cpp59 if( semaphore.post() == 0 ) {
70 if( semaphore.post() == 0 ) {
86 if( semaphore.post() == 0 ) {
97 if( semaphore.post() == 0 ) {
/gem5/ext/systemc/src/sysc/communication/
H A Dsc_semaphore_if.h47 // the classical operations: wait(), trywait(), and post()
56 virtual int post() = 0;
H A Dsc_semaphore.h66 virtual int post();
H A Dsc_semaphore.cpp111 sc_semaphore::post() function in class:sc_core::sc_semaphore
/gem5/src/systemc/tests/systemc/communication/sc_semaphore/test02/
H A Dtest02.cpp59 if( semaphore->post() == 0 ) {
70 if( semaphore->post() == 0 ) {
101 if( semaphore->post() == 0 ) {
112 if( semaphore->post() == 0 ) {
/gem5/src/arch/mips/
H A Dinterrupts.hh68 // post(int int_num, int index) is responsible
74 void post(int int_num, ThreadContext *tc);
75 void post(int int_num, int index);
H A Dinterrupts.cc59 Interrupts::post(int int_num, ThreadContext* tc) function in class:MipsISA::Interrupts
71 Interrupts::post(int int_num, int index) function in class:MipsISA::Interrupts
/gem5/src/arch/power/
H A Dinterrupts.hh67 post(int int_num, int index) function in class:PowerISA::Interrupts
69 panic("Interrupts::post not implemented.\n");
/gem5/src/systemc/channel/
H A Dsc_semaphore.cc72 sc_semaphore::post() function in class:sc_core::sc_semaphore
/gem5/src/systemc/tests/systemc/communication/sc_semaphore/test03/
H A Dtest_sem.cpp76 sem_1.post();
/gem5/src/dev/mips/
H A Dmalta_cchip.cc114 malta->intrctrl->post(i, interrupt, 0);
/gem5/src/arch/arm/insts/
H A Dmacromem.cc249 bool post = (mode == AddrMd_PostIndex); local
254 numMicroops = (post ? 0 : 1) + ((size + 4) / 8) + (writeback ? 1 : 0);
256 numMicroops = (post ? 0 : 1) + (size / 4) + (writeback ? 1 : 0);
264 if (!post) {
266 post ? 0 : imm);
273 post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
275 post ? rn : INTREG_UREG0, 16, noAlloc, exclusive, acrel);
278 post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
280 post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
282 post
[all...]
/gem5/src/dev/alpha/
H A Dtsunami_cchip.cc230 tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
257 //If it is bit 12-15, this is an IPI post
323 tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
438 tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
442 warn("post IPI for CPU=%d, but IPI already\n", cpunum);
461 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
479 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
/gem5/src/arch/riscv/
H A Dinterrupts.hh108 post(int int_num, int index) function in class:RiscvISA::Interrupts
/gem5/src/dev/sparc/
H A Diob.cc273 ic->post(intMan[devid].cpu, SparcISA::IT_INT_VEC, intMan[devid].vector);
288 ic->post(cpu_id, SparcISA::IT_INT_VEC, vector);
326 ic->post(cpu_id, SparcISA::IT_INT_VEC, jIntVec);
/gem5/src/arch/alpha/
H A Dinterrupts.hh84 post(int int_num, int index) function in class:AlphaISA::Interrupts
/gem5/src/arch/sparc/
H A Dinterrupts.hh102 post(int int_num, int index) function in class:SparcISA::Interrupts
/gem5/src/arch/x86/
H A Dinterrupts.hh283 post(int int_num, int index) function in class:X86ISA::Interrupts
285 panic("Interrupts::post unimplemented!\n");
/gem5/src/arch/arm/
H A Dinterrupts.hh90 post(int int_num, int index) function in class:ArmISA::Interrupts

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