/gem5/src/cpu/ |
H A D | intr_control.hh | 50 void post(int cpu_id, int int_num, int index); 59 post(int int_num, int index = 0) function in class:IntrControl 61 post(0, int_num, index);
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H A D | intr_control_noisa.cc | 41 IntrControl::post(int cpu_id, int int_num, int index) function in class:IntrControl
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H A D | intr_control.cc | 50 IntrControl::post(int cpu_id, int int_num, int index) function in class:IntrControl 52 DPRINTF(IntrControl, "post %d:%d (cpu %d)\n", int_num, index, cpu_id);
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H A D | base.hh | 240 interrupts[tid]->post(int_num, index);
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/gem5/src/systemc/ext/channel/ |
H A D | sc_semaphore_if.hh | 43 virtual int post() = 0;
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H A D | sc_semaphore.hh | 48 virtual int post();
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/gem5/src/systemc/tests/systemc/communication/sc_semaphore/test01/ |
H A D | test01.cpp | 59 if( semaphore.post() == 0 ) { 70 if( semaphore.post() == 0 ) { 86 if( semaphore.post() == 0 ) { 97 if( semaphore.post() == 0 ) {
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/gem5/ext/systemc/src/sysc/communication/ |
H A D | sc_semaphore_if.h | 47 // the classical operations: wait(), trywait(), and post() 56 virtual int post() = 0;
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H A D | sc_semaphore.h | 66 virtual int post();
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H A D | sc_semaphore.cpp | 111 sc_semaphore::post() function in class:sc_core::sc_semaphore
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/gem5/src/systemc/tests/systemc/communication/sc_semaphore/test02/ |
H A D | test02.cpp | 59 if( semaphore->post() == 0 ) { 70 if( semaphore->post() == 0 ) { 101 if( semaphore->post() == 0 ) { 112 if( semaphore->post() == 0 ) {
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/gem5/src/arch/mips/ |
H A D | interrupts.hh | 68 // post(int int_num, int index) is responsible 74 void post(int int_num, ThreadContext *tc); 75 void post(int int_num, int index);
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H A D | interrupts.cc | 59 Interrupts::post(int int_num, ThreadContext* tc) function in class:MipsISA::Interrupts 71 Interrupts::post(int int_num, int index) function in class:MipsISA::Interrupts
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/gem5/src/arch/power/ |
H A D | interrupts.hh | 67 post(int int_num, int index) function in class:PowerISA::Interrupts 69 panic("Interrupts::post not implemented.\n");
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/gem5/src/systemc/channel/ |
H A D | sc_semaphore.cc | 72 sc_semaphore::post() function in class:sc_core::sc_semaphore
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/gem5/src/systemc/tests/systemc/communication/sc_semaphore/test03/ |
H A D | test_sem.cpp | 76 sem_1.post();
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/gem5/src/dev/mips/ |
H A D | malta_cchip.cc | 114 malta->intrctrl->post(i, interrupt, 0);
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/gem5/src/arch/arm/insts/ |
H A D | macromem.cc | 249 bool post = (mode == AddrMd_PostIndex); local 254 numMicroops = (post ? 0 : 1) + ((size + 4) / 8) + (writeback ? 1 : 0); 256 numMicroops = (post ? 0 : 1) + (size / 4) + (writeback ? 1 : 0); 264 if (!post) { 266 post ? 0 : imm); 273 post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel); 275 post ? rn : INTREG_UREG0, 16, noAlloc, exclusive, acrel); 278 post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel); 280 post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel); 282 post [all...] |
/gem5/src/dev/alpha/ |
H A D | tsunami_cchip.cc | 230 tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 257 //If it is bit 12-15, this is an IPI post 323 tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 438 tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0); 442 warn("post IPI for CPU=%d, but IPI already\n", cpunum); 461 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0); 479 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
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/gem5/src/arch/riscv/ |
H A D | interrupts.hh | 108 post(int int_num, int index) function in class:RiscvISA::Interrupts
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/gem5/src/dev/sparc/ |
H A D | iob.cc | 273 ic->post(intMan[devid].cpu, SparcISA::IT_INT_VEC, intMan[devid].vector); 288 ic->post(cpu_id, SparcISA::IT_INT_VEC, vector); 326 ic->post(cpu_id, SparcISA::IT_INT_VEC, jIntVec);
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/gem5/src/arch/alpha/ |
H A D | interrupts.hh | 84 post(int int_num, int index) function in class:AlphaISA::Interrupts
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/gem5/src/arch/sparc/ |
H A D | interrupts.hh | 102 post(int int_num, int index) function in class:SparcISA::Interrupts
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/gem5/src/arch/x86/ |
H A D | interrupts.hh | 283 post(int int_num, int index) function in class:X86ISA::Interrupts 285 panic("Interrupts::post unimplemented!\n");
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/gem5/src/arch/arm/ |
H A D | interrupts.hh | 90 post(int int_num, int index) function in class:ArmISA::Interrupts
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