Searched refs:mtype (Results 1 - 10 of 10) sorted by relevance
/gem5/src/mem/slicc/ast/ |
H A D | MachineAST.py | 32 def __init__(self, slicc, mtype, pairs_ast, config_parameters, decls): 35 self.ident = mtype.value 73 mtype = self.ident 75 if not machine_type.checkEnum(mtype): 76 self.error("Duplicate machine name: %s:%s" % (machine_type, mtype))
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/gem5/src/arch/arm/ |
H A D | stage2_lookup.cc | 115 if (stage2Te->mtype == TlbEntry::MemoryType::StronglyOrdered || 116 stage1Te.mtype == TlbEntry::MemoryType::StronglyOrdered) { 117 stage1Te.mtype = TlbEntry::MemoryType::StronglyOrdered; 118 } else if (stage2Te->mtype == TlbEntry::MemoryType::Device || 119 stage1Te.mtype == TlbEntry::MemoryType::Device) { 120 stage1Te.mtype = TlbEntry::MemoryType::Device; 122 stage1Te.mtype = TlbEntry::MemoryType::Normal; 125 if (stage1Te.mtype == TlbEntry::MemoryType::Normal) {
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H A D | pagetable.hh | 122 MemoryType mtype; member in struct:ArmISA::TlbEntry 139 bool nonCacheable; // Can we wrap this in mtype? 155 domain(DomainType::Client), mtype(MemoryType::StronglyOrdered), 170 domain(DomainType::Client), mtype(MemoryType::StronglyOrdered), 311 SERIALIZE_ENUM(mtype); variable 341 UNSERIALIZE_ENUM(mtype); variable
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H A D | table_walker.cc | 1037 te.mtype = TlbEntry::MemoryType::StronglyOrdered; 1044 te.mtype = TlbEntry::MemoryType::Device; 1050 te.mtype = TlbEntry::MemoryType::Normal; 1056 te.mtype = TlbEntry::MemoryType::Normal; 1063 te.mtype = TlbEntry::MemoryType::Normal; 1075 te.mtype = TlbEntry::MemoryType::Normal; 1082 te.mtype = TlbEntry::MemoryType::Device; 1091 te.mtype = TlbEntry::MemoryType::Normal; 1159 te.mtype = TlbEntry::MemoryType::StronglyOrdered; 1168 te.mtype [all...] |
H A D | tlb.cc | 628 (te->mtype != TlbEntry::MemoryType::Normal)) { 638 if (te->mtype != TlbEntry::MemoryType::Normal) { 814 (te->mtype != TlbEntry::MemoryType::Normal)) { 824 if (te->mtype != TlbEntry::MemoryType::Normal) { 1113 temp_te.mtype = is_fetch ? TlbEntry::MemoryType::Normal 1120 temp_te.mtype = TlbEntry::MemoryType::Normal; 1153 "outerAttrs: %d, mtype: %d, isStage2: %d\n", 1155 static_cast<uint8_t>(te->mtype), isStage2); 1164 if (te->mtype != TlbEntry::MemoryType::Normal) 1174 (te->mtype ! [all...] |
/gem5/src/mem/ruby/network/ |
H A D | Network.cc | 199 Network::addressToNodeID(Addr addr, MachineType mtype) argument 203 const auto &matching_ranges = addrMap.equal_range(mtype); 213 return MachineType_base_count(mtype);
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H A D | Network.hh | 135 NodeID addressToNodeID(Addr addr, MachineType mtype);
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/gem5/src/mem/ruby/slicc_interface/ |
H A D | AbstractController.cc | 366 AbstractController::mapAddressToMachine(Addr addr, MachineType mtype) const 368 NodeID node = m_net_ptr->addressToNodeID(addr, mtype); 369 MachineID mach = {mtype, node};
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H A D | AbstractController.hh | 169 MachineID mapAddressToMachine(Addr addr, MachineType mtype) const;
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/gem5/ext/ply/ply/ |
H A D | cpp.py | 781 mtype = linetok[1] 783 mtype = None 784 if not mtype: 787 elif mtype.type in self.t_WS: 791 elif mtype.value == '(':
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