Searched refs:cam (Results 1 - 5 of 5) sorted by relevance

/gem5/ext/mcpat/cacti/
H A Dsubarray.cc60 } else { //cam fa
147 C_wl_cam = (gate_C_pass(g_tp.cam.cell_a_w,
148 (g_tp.cam.b_w - 2 * g_tp.cam.cell_a_w) /
181 C_b_row_drain_C = drain_C_(g_tp.cam.cell_a_w, NCH, 1, 0, cam_cell.w, false, true) / 2.0; // due to shared contact
H A Dparameter.h233 MemoryType cam; member in class:TechnologyParameter
268 cam.reset();
H A Dparameter.cc237 //Not fully_asso nor cam
268 else {//either fully-asso or cam
321 cam_cell.h = g_tp.cam.b_h + 2 * wire_local.pitch *
325 cam_cell.w = g_tp.cam.b_w + 2 * wire_local.pitch *
404 double Cbitrow_drain_cap = drain_C_(g_tp.cam.cell_a_w, NCH, 1, 0, cam_cell.w, false, true) / 2.0;//TODO: comment out these two lines
H A Dmat.cc517 //TODO: this is just for compute plain read/write energy for fa and cam, plain read/write access timing need to be revisited.
747 Wdummyn = g_tp.cam.cell_nmos_w;
794 + log(g_tp.cam.Vbitpre) * (R_bl_precharge * C_bl + R_bl * C_bl / 2);
836 + log(g_tp.cam.Vbitpre) * (R_ml_precharge * C_ml + R_ml * C_ml / 2);
922 delay_hit_miss_reset = log(g_tp.cam.Vbitpre) *
949 double Iport = cmos_Isub_leakage(g_tp.cam.cell_a_w, 0, 1, nmos, false, true);//TODO: how much is the idle time? just by *2?
950 double Iport_erp = cmos_Isub_leakage(g_tp.cam.cell_a_w, 0, 2, nmos, false, true);
951 double Icell = cmos_Isub_leakage(g_tp.cam.cell_nmos_w, g_tp.cam.cell_pmos_w,
983 double Ig_port_erp = cmos_Ig_leakage(g_tp.cam
[all...]
H A Dtechnology.cc1710 g_tp.cam.cell_a_w += curr_alpha * curr_Wmemcella_cam;//sheng
1711 g_tp.cam.cell_pmos_w += curr_alpha * curr_Wmemcellpmos_cam;
1712 g_tp.cam.cell_nmos_w += curr_alpha * curr_Wmemcellnmos_cam;
1791 g_tp.cam.b_w = sqrt(area_cell_cam / (asp_ratio_cell_cam));//Sheng
1792 g_tp.cam.b_h = asp_ratio_cell_cam * g_tp.cam.b_w;
1796 g_tp.cam.Vbitpre = vdd[ram_cell_tech_type];//Sheng

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