Searched hist:9105 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/mem/ruby/system/
H A DSConscriptdiff 9105:b576c490e7d1 Wed Jul 11 01:51:00 EDT 2012 Brad Beckmann <Brad.Beckmann@amd.com> ruby: banked cache array resource model

This patch models a cache as separate tag and data arrays. The patch exposes
the banked array as another resource that is checked by SLICC before a
transition is allowed to execute. This is similar to how TBE entries and slots
in output ports are modeled.
/gem5/src/mem/
H A DSConscriptdiff 9105:b576c490e7d1 Wed Jul 11 01:51:00 EDT 2012 Brad Beckmann <Brad.Beckmann@amd.com> ruby: banked cache array resource model

This patch models a cache as separate tag and data arrays. The patch exposes
the banked array as another resource that is checked by SLICC before a
transition is allowed to execute. This is similar to how TBE entries and slots
in output ports are modeled.
/gem5/src/mem/slicc/symbols/
H A DStateMachine.pydiff 9105:b576c490e7d1 Wed Jul 11 01:51:00 EDT 2012 Brad Beckmann <Brad.Beckmann@amd.com> ruby: banked cache array resource model

This patch models a cache as separate tag and data arrays. The patch exposes
the banked array as another resource that is checked by SLICC before a
transition is allowed to execute. This is similar to how TBE entries and slots
in output ports are modeled.

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