Searched hist:7348 (Results 1 - 3 of 3) sorted by relevance
/gem5/src/arch/power/ | ||
H A D | PowerTLB.py | diff 12433:b166ca57bf0e Mon Jan 08 22:07:00 EST 2018 Gabe Black <gabeblack@google.com> arm, power: Make the python TLB simobjects inherit from BaseTLB. These were still inheriting from SimObject instead of BaseTLB, making them incompatible with parameters which expect a BaseTLB. Change-Id: I05115cc5515f745fdeb85e4dea8eded613647e40 Reviewed-on: https://gem5-review.googlesource.com/7348 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/src/arch/arm/ | ||
H A D | ArmTLB.py | diff 12433:b166ca57bf0e Mon Jan 08 22:07:00 EST 2018 Gabe Black <gabeblack@google.com> arm, power: Make the python TLB simobjects inherit from BaseTLB. These were still inheriting from SimObject instead of BaseTLB, making them incompatible with parameters which expect a BaseTLB. Change-Id: I05115cc5515f745fdeb85e4dea8eded613647e40 Reviewed-on: https://gem5-review.googlesource.com/7348 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | isa.hh | diff 7348:c8103c298d68 Wed Jun 02 01:58:00 EDT 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add a traceflag to print cpsr |
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