Searched hist:5002 (Results 1 - 4 of 4) sorted by relevance
| /gem5/util/ | ||
| H A D | protolib.py | diff 12210:4c6eb3ea3e1a Wed Oct 04 22:28:00 EDT 2017 Gabe Black <gabeblack@google.com> misc: Small style fix in _EncodeVarint32. Added spaces around the '|' operator. Change-Id: I5cb82b98e7d2769605cde141f76a62a6e3c6570d Reviewed-on: https://gem5-review.googlesource.com/5002 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/x86/insts/ | ||
| H A D | microldstop.hh | diff 5002:1b540e93ad34 Sun Aug 26 23:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Remove x86 code that attempted to fix misaligned accesses. |
| /gem5/src/cpu/testers/traffic_gen/ | ||
| H A D | traffic_gen.cc | diff 10138:0e40c53fe85c Sun Mar 23 11:11:00 EDT 2014 Neha Agarwal <neha.agarwal@arm.com> cpu: DRAM Traffic Generator This patch enables a new 'DRAM' mode to the existing traffic generator, catered to generate specific requests to DRAM based on required hit length (stride size) and bank utilization. It is an add on to the Random mode. The basic idea is to control how many successive packets target the same page, and how many banks are being used in parallel. This gives a two-dimensional space that stresses different aspects of the DRAM timing. The configuration file needed to use this patch has to be changed as follow: (reference to Random Mode, LPDDR3 memory type) 'STATE 0 10000000000 RANDOM 50 0 134217728 64 3004 5002 0' -> 'STATE 0 10000000000 DRAM 50 0 134217728 32 3004 5002 0 96 1024 8 6 1' The last 4 parameters to be added are: <stride size (bytes), page size(bytes), number of banks available in DRAM, number of banks to be utilized, address mapping scheme> The address mapping information is used to get the stride address stream of the specified size and to know where to find the bank bits. The configuration file has a parameter where '0'-> RoCoRaBaCh, '1'-> RoRaBaCoCh/RoRaBaChCo address-mapping schemes. Note that the generator currently assumes a single channel and a single rank. This is to avoid overwhelming the traffic generator with information about the memory organisation. diff 10138:0e40c53fe85c Sun Mar 23 11:11:00 EDT 2014 Neha Agarwal <neha.agarwal@arm.com> cpu: DRAM Traffic Generator This patch enables a new 'DRAM' mode to the existing traffic generator, catered to generate specific requests to DRAM based on required hit length (stride size) and bank utilization. It is an add on to the Random mode. The basic idea is to control how many successive packets target the same page, and how many banks are being used in parallel. This gives a two-dimensional space that stresses different aspects of the DRAM timing. The configuration file needed to use this patch has to be changed as follow: (reference to Random Mode, LPDDR3 memory type) 'STATE 0 10000000000 RANDOM 50 0 134217728 64 3004 5002 0' -> 'STATE 0 10000000000 DRAM 50 0 134217728 32 3004 5002 0 96 1024 8 6 1' The last 4 parameters to be added are: <stride size (bytes), page size(bytes), number of banks available in DRAM, number of banks to be utilized, address mapping scheme> The address mapping information is used to get the stride address stream of the specified size and to know where to find the bank bits. The configuration file has a parameter where '0'-> RoCoRaBaCh, '1'-> RoRaBaCoCh/RoRaBaChCo address-mapping schemes. Note that the generator currently assumes a single channel and a single rank. This is to avoid overwhelming the traffic generator with information about the memory organisation. |
| /gem5/src/arch/x86/isa/microops/ | ||
| H A D | ldstop.isa | diff 5002:1b540e93ad34 Sun Aug 26 23:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Remove x86 code that attempted to fix misaligned accesses. |
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