Searched hist:4046 (Results 1 - 16 of 16) sorted by relevance
/gem5/src/mem/cache/compressors/ | ||
H A D | base.cc | diff 13943:4046b0c547be Tue May 29 11:30:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Add compression stats Add compression statistics to the compressors. It tracks the number of blocks that can fit into a certain power of two size, and the number of decompressions. For example, if a block is compressed to 100 bits, it will belong to the 128-bits compression size. Although it could also fit bigger sizes, they are not taken into account for the stats (i.e., the 100-bit compression will fit only the 128-bits size, not 256 or higher). We save stats for compressions that fail (i.e., compressed size is bigger than original cache line size). Change-Id: Idab71a40a660e33259908ccd880e42a880b5ee06 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11103 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | base.hh | diff 13943:4046b0c547be Tue May 29 11:30:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Add compression stats Add compression statistics to the compressors. It tracks the number of blocks that can fit into a certain power of two size, and the number of decompressions. For example, if a block is compressed to 100 bits, it will belong to the 128-bits compression size. Although it could also fit bigger sizes, they are not taken into account for the stats (i.e., the 100-bit compression will fit only the 128-bits size, not 256 or higher). We save stats for compressions that fail (i.e., compressed size is bigger than original cache line size). Change-Id: Idab71a40a660e33259908ccd880e42a880b5ee06 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11103 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
/gem5/src/base/ | ||
H A D | trace.cc | diff 4046:ef34b290091e Sat Feb 10 18:14:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Clean up tracing stuff more, get rid of the trace log since its not all that useful. Fix a few bugs with python/C++ integration. |
H A D | trace.hh | diff 4046:ef34b290091e Sat Feb 10 18:14:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Clean up tracing stuff more, get rid of the trace log since its not all that useful. Fix a few bugs with python/C++ integration. |
/gem5/src/kern/linux/ | ||
H A D | printk.cc | diff 4046:ef34b290091e Sat Feb 10 18:14:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Clean up tracing stuff more, get rid of the trace log since its not all that useful. Fix a few bugs with python/C++ integration. |
/gem5/src/cpu/o3/ | ||
H A D | rename_map.cc | diff 4030:4046b2213995 Fri Mar 23 11:22:00 EDT 2007 Kevin Lim <ktlim@umich.edu> A couple of minor fixes. 1. Set CPU ID in all modes for the O3 CPU. 2. Use nextCycle() function to prevent phase drift in O3 CPU. 3. Remove assertion in rename map that is no longer true. src/cpu/o3/alpha/cpu_builder.cc: Allow for CPU id in all modes, not just full system. Also include a parameter that was left out by accident. src/cpu/o3/alpha/cpu_impl.hh: Set the CPU ID properly. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: Use nextCycle() function so that the CPU does not get out of phase when starting up from quiesces. src/cpu/o3/rename_map.cc: Remove assertion that is no longer true. tests/configs/o3-timing.py: Set CPU's id to 0. |
H A D | commit_impl.hh | diff 4046:ef34b290091e Sat Feb 10 18:14:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Clean up tracing stuff more, get rid of the trace log since its not all that useful. Fix a few bugs with python/C++ integration. |
H A D | cpu.hh | diff 4030:4046b2213995 Fri Mar 23 11:22:00 EDT 2007 Kevin Lim <ktlim@umich.edu> A couple of minor fixes. 1. Set CPU ID in all modes for the O3 CPU. 2. Use nextCycle() function to prevent phase drift in O3 CPU. 3. Remove assertion in rename map that is no longer true. src/cpu/o3/alpha/cpu_builder.cc: Allow for CPU id in all modes, not just full system. Also include a parameter that was left out by accident. src/cpu/o3/alpha/cpu_impl.hh: Set the CPU ID properly. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: Use nextCycle() function so that the CPU does not get out of phase when starting up from quiesces. src/cpu/o3/rename_map.cc: Remove assertion that is no longer true. tests/configs/o3-timing.py: Set CPU's id to 0. |
H A D | cpu.cc | diff 4030:4046b2213995 Fri Mar 23 11:22:00 EDT 2007 Kevin Lim <ktlim@umich.edu> A couple of minor fixes. 1. Set CPU ID in all modes for the O3 CPU. 2. Use nextCycle() function to prevent phase drift in O3 CPU. 3. Remove assertion in rename map that is no longer true. src/cpu/o3/alpha/cpu_builder.cc: Allow for CPU id in all modes, not just full system. Also include a parameter that was left out by accident. src/cpu/o3/alpha/cpu_impl.hh: Set the CPU ID properly. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: Use nextCycle() function so that the CPU does not get out of phase when starting up from quiesces. src/cpu/o3/rename_map.cc: Remove assertion that is no longer true. tests/configs/o3-timing.py: Set CPU's id to 0. |
/gem5/src/cpu/ | ||
H A D | exetrace.hh | diff 4046:ef34b290091e Sat Feb 10 18:14:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Clean up tracing stuff more, get rid of the trace log since its not all that useful. Fix a few bugs with python/C++ integration. |
H A D | exetrace.cc | diff 4046:ef34b290091e Sat Feb 10 18:14:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Clean up tracing stuff more, get rid of the trace log since its not all that useful. Fix a few bugs with python/C++ integration. |
/gem5/tests/configs/ | ||
H A D | o3-timing.py | diff 4030:4046b2213995 Fri Mar 23 11:22:00 EDT 2007 Kevin Lim <ktlim@umich.edu> A couple of minor fixes. 1. Set CPU ID in all modes for the O3 CPU. 2. Use nextCycle() function to prevent phase drift in O3 CPU. 3. Remove assertion in rename map that is no longer true. src/cpu/o3/alpha/cpu_builder.cc: Allow for CPU id in all modes, not just full system. Also include a parameter that was left out by accident. src/cpu/o3/alpha/cpu_impl.hh: Set the CPU ID properly. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: Use nextCycle() function so that the CPU does not get out of phase when starting up from quiesces. src/cpu/o3/rename_map.cc: Remove assertion that is no longer true. tests/configs/o3-timing.py: Set CPU's id to 0. |
/gem5/src/sim/ | ||
H A D | main.cc | diff 4046:ef34b290091e Sat Feb 10 18:14:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Clean up tracing stuff more, get rid of the trace log since its not all that useful. Fix a few bugs with python/C++ integration. |
/gem5/src/python/m5/ | ||
H A D | main.py | diff 4046:ef34b290091e Sat Feb 10 18:14:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Clean up tracing stuff more, get rid of the trace log since its not all that useful. Fix a few bugs with python/C++ integration. |
/gem5/src/cpu/simple/ | ||
H A D | base.cc | diff 4046:ef34b290091e Sat Feb 10 18:14:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Clean up tracing stuff more, get rid of the trace log since its not all that useful. Fix a few bugs with python/C++ integration. |
/gem5/src/ | ||
H A D | SConscript | diff 4046:ef34b290091e Sat Feb 10 18:14:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Clean up tracing stuff more, get rid of the trace log since its not all that useful. Fix a few bugs with python/C++ integration. |
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