Searched hist:2965 (Results 1 - 6 of 6) sorted by relevance
| /gem5/src/arch/mips/isa/ | ||
| H A D | base.isa | diff 2965:82703e01285a Wed Jul 26 18:47:00 EDT 2006 Korey Sewell <ksewell@umich.edu> MIPS ISA runs 'hello world' in O3CPU ... src/arch/mips/isa/base.isa: special case syscall disasembly... maybe give own instruction class? src/arch/mips/isa/decoder.isa: add 'IsSerializeAfter' flag for syscall src/cpu/o3/commit.hh: Add skidBuffer to commit src/cpu/o3/commit_impl.hh: Use skidbuffer in MIPS ISA src/cpu/o3/fetch_impl.hh: Print name out when there is a fault src/cpu/o3/mips/cpu_impl.hh: change comment |
| H A D | decoder.isa | diff 2965:82703e01285a Wed Jul 26 18:47:00 EDT 2006 Korey Sewell <ksewell@umich.edu> MIPS ISA runs 'hello world' in O3CPU ... src/arch/mips/isa/base.isa: special case syscall disasembly... maybe give own instruction class? src/arch/mips/isa/decoder.isa: add 'IsSerializeAfter' flag for syscall src/cpu/o3/commit.hh: Add skidBuffer to commit src/cpu/o3/commit_impl.hh: Use skidbuffer in MIPS ISA src/cpu/o3/fetch_impl.hh: Print name out when there is a fault src/cpu/o3/mips/cpu_impl.hh: change comment |
| /gem5/src/cpu/o3/ | ||
| H A D | commit.hh | diff 2965:82703e01285a Wed Jul 26 18:47:00 EDT 2006 Korey Sewell <ksewell@umich.edu> MIPS ISA runs 'hello world' in O3CPU ... src/arch/mips/isa/base.isa: special case syscall disasembly... maybe give own instruction class? src/arch/mips/isa/decoder.isa: add 'IsSerializeAfter' flag for syscall src/cpu/o3/commit.hh: Add skidBuffer to commit src/cpu/o3/commit_impl.hh: Use skidbuffer in MIPS ISA src/cpu/o3/fetch_impl.hh: Print name out when there is a fault src/cpu/o3/mips/cpu_impl.hh: change comment |
| H A D | commit_impl.hh | diff 2965:82703e01285a Wed Jul 26 18:47:00 EDT 2006 Korey Sewell <ksewell@umich.edu> MIPS ISA runs 'hello world' in O3CPU ... src/arch/mips/isa/base.isa: special case syscall disasembly... maybe give own instruction class? src/arch/mips/isa/decoder.isa: add 'IsSerializeAfter' flag for syscall src/cpu/o3/commit.hh: Add skidBuffer to commit src/cpu/o3/commit_impl.hh: Use skidbuffer in MIPS ISA src/cpu/o3/fetch_impl.hh: Print name out when there is a fault src/cpu/o3/mips/cpu_impl.hh: change comment |
| H A D | fetch_impl.hh | diff 2965:82703e01285a Wed Jul 26 18:47:00 EDT 2006 Korey Sewell <ksewell@umich.edu> MIPS ISA runs 'hello world' in O3CPU ... src/arch/mips/isa/base.isa: special case syscall disasembly... maybe give own instruction class? src/arch/mips/isa/decoder.isa: add 'IsSerializeAfter' flag for syscall src/cpu/o3/commit.hh: Add skidBuffer to commit src/cpu/o3/commit_impl.hh: Use skidbuffer in MIPS ISA src/cpu/o3/fetch_impl.hh: Print name out when there is a fault src/cpu/o3/mips/cpu_impl.hh: change comment |
| /gem5/src/dev/arm/ | ||
| H A D | RealView.py | diff 12006:aebe66ac7a3d Fri Apr 28 05:55:00 EDT 2017 Andreas Sandberg <andreas.sandberg@arm.com> arm: Enable m5ops by default for VExpress_GEM5_V1 Allocate 0x10010000-0x1001ffff for m5 pseudo-ops. This range is a part of the CS5 address range in the RS1/RS2 memory map. Change-Id: Ica45cd53bc4ebb62966afa099fa465e27fb0452c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2965 |
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