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/gem5/src/arch/generic/
H A Dvec_reg.hh12108:885cbffd3ab0 Wed Apr 05 14:20:00 EDT 2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> arch: added generic vector register

This commit adds a new generic vector register to have a cleaner
implementation of SIMD ISAs.

Nathanael's idea, Rekai's implementation.

Change-Id: I60b250bba6423153b7e04d2e6988d517a70a3e6b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2704
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/cpu/checker/
H A Dcpu.ccdiff 2704:731cd38be7f5 Mon Jun 12 19:11:00 EDT 2006 Kevin Lim <ktlim@umich.edu> Fixes for checker. The RC/RS instructions check the interrupt flag, which isn't verifiable by the checker.

src/arch/alpha/isa/decoder.isa:
src/cpu/checker/cpu.cc:
Fixes for checker.
/gem5/src/arch/alpha/isa/
H A Ddecoder.isadiff 2704:731cd38be7f5 Mon Jun 12 19:11:00 EDT 2006 Kevin Lim <ktlim@umich.edu> Fixes for checker. The RC/RS instructions check the interrupt flag, which isn't verifiable by the checker.

src/arch/alpha/isa/decoder.isa:
src/cpu/checker/cpu.cc:
Fixes for checker.

Completed in 70 milliseconds