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| /gem5/src/mem/slicc/ast/ | ||
| H A D | CheckProbeStatementAST.py | 14097:1f8f4c773c49 Wed Feb 27 16:25:00 EST 2019 Pouya Fotouhi <pfotouhi@ucdavis.edu> mem-ruby: Adding a new slicc statement - to not evict locked cachelines Ruby caches block incoming ports with messages on a locked address to make sure the line would not be replaced by others. But they do not check the lock upon capacity/conflict misses. This change adds a new slicc statement "check_on_cache_probe" which takes two arguments (mandatoryQueue for the controller, and the line subject to eviction - i.e. address returned by cacheProbe). If the line is locked, incoming message is delayed for 1 cycle and the controller skips this request (i.e. does not trigger an event). Coherence protocols should be updated accordingly. One use case for MESI Two Level will be added in a separate change. Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Change-Id: I79ca2d45518de7a4e382b520a11f8e221b0cb803 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16808 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | __init__.py | diff 14097:1f8f4c773c49 Wed Feb 27 16:25:00 EST 2019 Pouya Fotouhi <pfotouhi@ucdavis.edu> mem-ruby: Adding a new slicc statement - to not evict locked cachelines Ruby caches block incoming ports with messages on a locked address to make sure the line would not be replaced by others. But they do not check the lock upon capacity/conflict misses. This change adds a new slicc statement "check_on_cache_probe" which takes two arguments (mandatoryQueue for the controller, and the line subject to eviction - i.e. address returned by cacheProbe). If the line is locked, incoming message is delayed for 1 cycle and the controller skips this request (i.e. does not trigger an event). Coherence protocols should be updated accordingly. One use case for MESI Two Level will be added in a separate change. Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Change-Id: I79ca2d45518de7a4e382b520a11f8e221b0cb803 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16808 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| /gem5/src/mem/slicc/ | ||
| H A D | parser.py | diff 14097:1f8f4c773c49 Wed Feb 27 16:25:00 EST 2019 Pouya Fotouhi <pfotouhi@ucdavis.edu> mem-ruby: Adding a new slicc statement - to not evict locked cachelines Ruby caches block incoming ports with messages on a locked address to make sure the line would not be replaced by others. But they do not check the lock upon capacity/conflict misses. This change adds a new slicc statement "check_on_cache_probe" which takes two arguments (mandatoryQueue for the controller, and the line subject to eviction - i.e. address returned by cacheProbe). If the line is locked, incoming message is delayed for 1 cycle and the controller skips this request (i.e. does not trigger an event). Coherence protocols should be updated accordingly. One use case for MESI Two Level will be added in a separate change. Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Change-Id: I79ca2d45518de7a4e382b520a11f8e221b0cb803 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16808 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
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