Searched hist:12711 (Results 1 - 1 of 1) sorted by relevance

/gem5/src/arch/arm/
H A Dmiscregs.ccdiff 12711:0b3d48de58e2 Wed May 09 12:56:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation defined

In the AArch64 ISA, S3_<op1>_<Cn>_<Cm>_<op2> refers to a pool
of implementation defined registers, provided that reg numbers
are in the following range:

<op1> is in the range 0 - 7
<CRn> can take the values 11, 15
<CRm> is in the range 0 - 15
<op2> is in the range 0 - 7

Change-Id: I7edd013e5cea4887f5e4c5a81f4835b7de93bd50
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10501
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

Completed in 17 milliseconds