Searched hist:11749 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/mem/cache/
H A Dcache.ccdiff 11749:3b2cb95f48ed Mon Dec 05 16:48:00 EST 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: Allow non invalidating snoops on an InvalidateReq MSHR

This patch changes an assertion that previously assumed that a non
invalidating snoop request should never be serviced by an
InvalidateReq MSHR. The MSHR serves as the ordering point for the
snooping packet. When the InvalidateResp reaches the cache the
snooping packet snoops the caches above to find the requested
block. One or more of the caches above will have the block since
earlier it has seen a WriteLineReq.

Change-Id: I0c147c8b5d5019e18bd34adf9af0fccfe431ae07
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
H A Dbase.ccdiff 12820:5d66b60a2c47 Fri Jul 13 09:21:00 EDT 2018 Robert Kovacsics <rmk35@cl.cam.ac.uk> mem-cache: Typo in comment: 'proceed' -> 'precede'

The writebacks happen before anything below, not after.

Change-Id: I7eaefbbf33aa17c496255dedd964a56118a28741
Reviewed-on: https://gem5-review.googlesource.com/11749
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

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