Searched hist:10481 (Results 1 - 7 of 7) sorted by relevance
/gem5/src/gpu-compute/ | ||
H A D | tlb_coalescer.cc | diff 12717:2e2c211644d2 Fri Apr 27 14:56:00 EDT 2018 Brandon Potter <brandon.potter@amd.com> gpu-compute: use X86ISA::TlbEntry over GpuTlbEntry GpuTlbEntry was derived from a vanilla X86ISA::TlbEntry definition. It wrapped the class and included an extra member "valid". This member was intended to report on the validity of the entry, however it introduced bugs when folks forgot to set field properly in the code. So, instead of keeping the extra field which we might forget to set, we track validity by using nullptr for invalid tlb entries (as the tlb entries are dynamically allocated). This saves on the extra class definition and prevents bugs creeping into the code since the checks are intrinsically tied into accessing any of the X86ISA::TlbEntry members. This changeset fixes the issues introduced by a8d030522, a4e722725, and 2a15bfd79. Change-Id: I30ebe3ec223fb833f3795bf0403d0016ac9a8bc2 Reviewed-on: https://gem5-review.googlesource.com/10481 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> |
H A D | gpu_tlb.hh | diff 12717:2e2c211644d2 Fri Apr 27 14:56:00 EDT 2018 Brandon Potter <brandon.potter@amd.com> gpu-compute: use X86ISA::TlbEntry over GpuTlbEntry GpuTlbEntry was derived from a vanilla X86ISA::TlbEntry definition. It wrapped the class and included an extra member "valid". This member was intended to report on the validity of the entry, however it introduced bugs when folks forgot to set field properly in the code. So, instead of keeping the extra field which we might forget to set, we track validity by using nullptr for invalid tlb entries (as the tlb entries are dynamically allocated). This saves on the extra class definition and prevents bugs creeping into the code since the checks are intrinsically tied into accessing any of the X86ISA::TlbEntry members. This changeset fixes the issues introduced by a8d030522, a4e722725, and 2a15bfd79. Change-Id: I30ebe3ec223fb833f3795bf0403d0016ac9a8bc2 Reviewed-on: https://gem5-review.googlesource.com/10481 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> |
H A D | gpu_tlb.cc | diff 12717:2e2c211644d2 Fri Apr 27 14:56:00 EDT 2018 Brandon Potter <brandon.potter@amd.com> gpu-compute: use X86ISA::TlbEntry over GpuTlbEntry GpuTlbEntry was derived from a vanilla X86ISA::TlbEntry definition. It wrapped the class and included an extra member "valid". This member was intended to report on the validity of the entry, however it introduced bugs when folks forgot to set field properly in the code. So, instead of keeping the extra field which we might forget to set, we track validity by using nullptr for invalid tlb entries (as the tlb entries are dynamically allocated). This saves on the extra class definition and prevents bugs creeping into the code since the checks are intrinsically tied into accessing any of the X86ISA::TlbEntry members. This changeset fixes the issues introduced by a8d030522, a4e722725, and 2a15bfd79. Change-Id: I30ebe3ec223fb833f3795bf0403d0016ac9a8bc2 Reviewed-on: https://gem5-review.googlesource.com/10481 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> |
H A D | compute_unit.cc | diff 12717:2e2c211644d2 Fri Apr 27 14:56:00 EDT 2018 Brandon Potter <brandon.potter@amd.com> gpu-compute: use X86ISA::TlbEntry over GpuTlbEntry GpuTlbEntry was derived from a vanilla X86ISA::TlbEntry definition. It wrapped the class and included an extra member "valid". This member was intended to report on the validity of the entry, however it introduced bugs when folks forgot to set field properly in the code. So, instead of keeping the extra field which we might forget to set, we track validity by using nullptr for invalid tlb entries (as the tlb entries are dynamically allocated). This saves on the extra class definition and prevents bugs creeping into the code since the checks are intrinsically tied into accessing any of the X86ISA::TlbEntry members. This changeset fixes the issues introduced by a8d030522, a4e722725, and 2a15bfd79. Change-Id: I30ebe3ec223fb833f3795bf0403d0016ac9a8bc2 Reviewed-on: https://gem5-review.googlesource.com/10481 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> |
/gem5/src/base/ | ||
H A D | addr_range.hh | diff 10481:59fb5779ec6e Thu Oct 16 05:49:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> misc: Move AddrRangeList from port.hh to addr_range.hh The new location seems like a better fit. The iterator typedefs are removed in favour of using C++11 auto. |
/gem5/src/mem/ | ||
H A D | port.hh | diff 10481:59fb5779ec6e Thu Oct 16 05:49:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> misc: Move AddrRangeList from port.hh to addr_range.hh The new location seems like a better fit. The iterator typedefs are removed in favour of using C++11 auto. |
/gem5/src/mem/ruby/system/ | ||
H A D | RubyPort.cc | diff 10481:59fb5779ec6e Thu Oct 16 05:49:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> misc: Move AddrRangeList from port.hh to addr_range.hh The new location seems like a better fit. The iterator typedefs are removed in favour of using C++11 auto. |
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