Searched defs:map (Results 1 - 17 of 17) sorted by relevance

/gem5/src/dev/x86/
H A DI8259.py35 map = {'I8259Master' : 0, variable in class:X86I8259CascadeMode
/gem5/ext/dsent/libutil/
H A DCalculator.cc47 evaluateString(const String& str_, const map<String, String> &config, DSENT::Model *ms_model, map<string, double> &outputs) argument
176 prim(istringstream& ist_, bool is_get_, const map<String, String> &config, DSENT::Model *ms_model) argument
220 term(istringstream& ist_, bool is_get_, const map<String, String> &config, DSENT::Model *ms_model) argument
245 expr(istringstream& ist_, bool is_get_, const map<String, String> &config, DSENT::Model *ms_model) argument
267 getEnvVar(const String& var_name_, const map<String, String> &config, DSENT::Model *ms_model) const argument
/gem5/src/arch/x86/bios/
H A DSMBios.py48 map = {'Unknown' : 2, variable in class:Characteristic
81 map = {'ACPI' : 0, variable in class:ExtCharacteristic
H A DIntelMP.py137 map = {'INT' : 0, variable in class:X86IntelMPInterruptType
144 map = {'ConformPolarity' : 0, variable in class:X86IntelMPPolarity
150 map = {'ConformTrigger' : 0, variable in class:X86IntelMPTriggerMode
196 map = {"IOAddress" : 0, variable in class:X86IntelMPAddressType
223 map = {"ISACompatible" : 0, variable in class:X86IntelMPRangeList
/gem5/src/mem/
H A Dpage_table.cc49 EmulationPageTable::map(Addr vaddr, Addr paddr, int64_t size, uint64_t flags) function in class:EmulationPageTable
/gem5/src/sim/
H A Deventq.cc321 std::unordered_map<long, bool> map; local
H A DProcess.py39 def map(self, vaddr, paddr, size, cacheable=False): member in class:Process
H A Dprocess.cc384 Process::map(Addr vaddr, Addr paddr, int size, bool cacheable) function in class:Process
/gem5/src/arch/arm/
H A DArmSystem.py48 map = { variable in class:ArmMachineType
/gem5/ext/dsent/
H A DDSENT.cc32 static void performTimingOpt(const map<String, String> &params, argument
95 static void reportTiming(const map<String, String> &params, Model *ms_model) argument
116 static Model *buildModel(const map<String, String> &params, argument
254 static TechModel* constructTechModel(const map<String, String>& params) argument
304 void run(const map<String, String> &params, Model *ms_model, argument
327 getEnvVar(const String& var_name_, const map<String, String> &config, Model *ms_model) const argument
/gem5/ext/pybind11/tests/
H A Dtest_sequences_and_iterators.cpp236 std::unordered_map<std::string, std::string> map; member in class:StringMap
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/gem5/src/gpu-compute/
H A Dhsail_code.hh207 std::map<std::string, Label> map; member in class:LabelMap
/gem5/src/mem/ruby/system/
H A DSequencer.cc659 operator<<(ostream &out, const std::unordered_map<KEY, VALUE> &map) argument
H A DGPUCoalescer.cc961 operator<<(ostream &out, const std::unordered_map<KEY, VALUE> &map) argument
/gem5/src/cpu/o3/
H A Drename_impl.hh1069 RenameMap *map = renameMap[tid]; local
1136 RenameMap *map = renameMap[tid]; local
/gem5/ext/pybind11/include/pybind11/
H A Deigen.h416 std::unique_ptr<MapType> map; member in struct:type_caster
/gem5/ext/googletest/googletest/src/
H A Dgtest-port.cc534 static ThreadIdToThreadLocals* map = new ThreadIdToThreadLocals; local

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