Searched refs:be (Results 1 - 17 of 17) sorted by relevance

/gem5/src/systemc/ext/utils/
H A Dendian.hh76 # error The file boost/detail/endian.hpp needs to be set up for your CPU type.
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64mi/
H A Daccess.S24 # after the pc is set to rs1, an access exception should be raised.
/gem5/system/alpha/console/
H A Ddbmentry.S14 * contributors may be used to endorse or promote products derived from
56 # This must be changed as well!
210 ret zero, (ra) # Should never be reached
/gem5/configs/ruby/
H A DAMD_Base_Constructor.py17 # contributors may be used to endorse or promote products derived from this
114 to be built.")
/gem5/src/mem/
H A Drequest.hh6 * not be construed as granting a license to any other intellectual
26 * contributors may be used to endorse or promote products derived from
66 * and Cache Occupancy. Having too many tasks seems to be a problem
67 * with vector stats. 1024 seems to be a reasonable number that
110 * @note Uncacheable accesses may be reordered by CPU models. The
111 * STRICT_ORDER flag should be set if such reordering is
116 * The request is required to be strictly ordered by <i>CPU
119 * A strictly ordered request is guaranteed to never be
142 * that locked accesses have to be made up of a locked load,
154 /** The request should be prefetche
646 setByteEnable(const std::vector<bool>& be) argument
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/gem5/ext/systemc/src/sysc/qt/md/
H A Dhppa.s68 copy %arg0,%r22 ; helper to be called by $$dyncall
153 copy %r15,%r22 ; function to be called by $$dyncall
214 ; take r22 to be our new base register.
H A Dksr1.s195 # and will consequently be the return value of the blocking routine.
248 # FPU registers don't need to be loaded, or will be loaded by an
291 # Store 8 registers at once...destination must be a multiple of 64
311 # Load 8 registers at once...source must be a multiple of 64
414 # will be executed. However, we don't know when we compile this code
H A Dhppa_b.s53 stwm %r3,64(%sp) ; store r3 (may be used by caller)
/gem5/src/arch/mips/
H A Dpra_constants.hh13 * contributors may be used to endorse or promote products derived from
222 Bitfield<15> be; member in namespace:MipsISA
H A Disa.cc13 * contributors may be used to endorse or promote products derived from
171 panic("CP state must be set before the following code is used");
194 cfg.be = cp.CP0_Config_BE;
329 // to be controlled on a per CPU model basis
473 // be overwritten. Make sure to handle those particular registers
/gem5/src/arch/riscv/
H A Dpra_constants.hh13 * contributors may be used to endorse or promote products derived from
222 Bitfield<15> be; member in namespace:RiscvISA
/gem5/ext/systemc/src/sysc/datatypes/int/
H A Dsc_nbcommon.inc845 // 3. u / v && u = v => u = 1 * u + 0 - u or v can be 1 or -1
846 // 4. u / v && u < v => u = 0 * v + u - u can be 1 or -1
847 // 5. u / v && u > v => u = q * v + r - v can be 1 or -1
1003 // 3. u % v && u = v => u = 1 * u + 0 - u or v can be 1 or -1
1004 // 4. u % v && u < v => u = 0 * v + u - u can be 1 or -1
1005 // 5. u % v && u > v => u = q * v + r - v can be 1 or -1
2531 // below can be converted to addition/subtraction and comparison
2662 // nbits can still be <= 0 because l and r have just been updated
2679 // The rest will be executed if u is not zero.
2733 // will be use
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/gem5/configs/common/
H A DHMC.py5 # not be construed as granting a license to any other intellectual
24 # contributors may be used to endorse or promote products derived from
114 # link can be connected to separate processor.
117 # connected.Through each crossbar only local vaults can be accessed. But to
123 # request can be forwarded to any other vault.
172 # link. This number should be adjusted to achive required bandwidth
178 # link. This number should be adjusted to achive required bandwidth
289 cache line size will be set to this value.\nDefault:\
428 # then it will be forward to correct xbar. Bridge is used to connect xbars
/gem5/src/mem/cache/prefetch/
H A DPrefetcher.py5 # not be construed as granting a license to any other intellectual
24 # contributors may be used to endorse or promote products derived from
100 raise TypeError("argument must be of SimObject type")
107 raise TypeError("argument must be a SimObject type")
133 # addresses generated by the prefetcher will be finally turned into
135 # - If set to 100, all candidates can be discarded (one request
136 # will always be allowed to be generated)
140 # remaining 60% will be generated depending on the current accuracy
142 that can be throttle
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/gem5/ext/pybind11/tests/
H A Dtest_sequences_and_iterators.cpp8 BSD-style license that can be found in the LICENSE file.
279 // kept here for illustrative purposes because there might be some use cases which
300 On the actual Sequence object, the iterator would be constructed as follows:
/gem5/configs/example/
H A Dread_config.py5 # not be construed as granting a license to any other intellectual
21 # contributors may be used to endorse or promote products derived from
39 # previous gem5 run to be read in and instantiated.
41 # This may be useful as a way of allowing variant run scripts (say,
70 # file elements. This could be moved into src/python/m5/params.py if
71 # reading .ini files from Python proves to be useful
105 # The string will be in tick/byte
112 # These parameters have trickier parsing from .ini files than might be
306 # This will be used to check that the next-to-be
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/gem5/util/streamline/
H A Dm5stats2streamline.py7 # not be construed as granting a license to any other intellectual
23 # contributors may be used to endorse or promote products derived from
42 # (Requires the gem5 runs to be run with ContextSwitchStatsDump enabled and
49 # <stat_config.ini>: .ini file that describes which stats to be included
50 # in conversion. Sample .ini files can be found in
60 # Subsequent versions should be backward compatible
76 (NOTE: Requires gem5 runs to be run with ContextSwitchStatsDump
82 Subsequent versions should be backward compatible
86 help=".ini file that describes which stats to be included \
87 in conversion. Sample .ini files can be foun
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