Searched refs:width_n (Results 1 - 3 of 3) sorted by relevance

/gem5/ext/mcpat/cacti/
H A Ddecoder.h227 double width_n[MAX_NUMBER_GATES_STAGE]; member in class:Driver
H A Ddecoder.cc1425 width_n[i] = 0;
1436 width_n[0] = g_tp.min_w_nmos_;
1439 double F = c_load / gate_C(width_n[0] + width_p[0], 0, is_dram_);
1444 width_n,
1460 rd = tr_R_on(width_n[i], NCH, 1, is_dram_);
1461 c_load = gate_C(width_n[i+1] + width_p[i+1], 0.0, is_dram_);
1463 drain_C_(width_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_);
1471 cmos_Isub_leakage(width_n[i], width_p[i], 1, inv, is_dram_) *
1474 cmos_Ig_leakage(width_n[i], width_p[i], 1, inv, is_dram_) *
1480 rd = tr_R_on(width_n[
[all...]
H A Dmat.cc488 rd = tr_R_on(ml_to_ram_wl_drv->width_n[k], NCH, 1, is_dram, false, true);
489 C_intrinsic = drain_C_(ml_to_ram_wl_drv->width_n[k], PCH, 1, 1, 4 *
491 drain_C_(ml_to_ram_wl_drv->width_n[k], NCH, 1, 1, 4 * cell.h,
897 c_gate_load = gate_C(ml_to_ram_wl_drv->width_n[0] + ml_to_ram_wl_drv->width_p[0], 0, is_dram);

Completed in 22 milliseconds