Searched refs:vecMode (Results 1 - 6 of 6) sorted by relevance

/gem5/src/cpu/o3/
H A Drename_map.cc119 vecMode = _mode;
139 if (vecMode == Enums::Elem) {
155 } else if (vecMode == Enums::Full) {
177 if (newVecMode == Enums::Elem && vecMode == Enums::Full) {
180 vecMode = Enums::Elem;
195 } else if (newVecMode == Enums::Full && vecMode == Enums::Elem) {
198 vecMode = Enums::Full;
H A Drename_map.hh196 VecMode vecMode;
237 assert(vecMode == Enums::Full);
240 assert(vecMode == Enums::Elem);
278 assert(vecMode == Enums::Full);
282 assert(vecMode == Enums::Elem);
323 assert(vecMode == Enums::Full);
328 assert(vecMode == Enums::Elem);
363 vecMode == Enums::Full ? vecMap.numFreeEntries()
372 return vecMode == Enums::Full
403 * depending on vecMode (vecto
[all...]
H A Dregfile.cc76 vecMode(vmode)
167 if (vecMode == Enums::Full)
H A Dcpu.cc114 vecMode(RenameMode<TheISA::ISA>::init(params->isa[0])),
120 vecMode),
235 vecMode);
238 &freeList, vecMode);
262 if (vecMode == Enums::Full) {
875 // We update vecMode only if there has been a change
876 if (new_mode != vecMode) {
877 vecMode = new_mode;
879 renameMap[tid].switchMode(vecMode);
880 commitRenameMap[tid].switchMode(vecMode);
[all...]
H A Dcpu.hh321 * The vecMode variable is updated and propagated to rename maps.
367 Enums::VecRegRenameMode vecRenameMode() const { return vecMode; }
371 { vecMode = vec_mode; }
575 Enums::VecRegRenameMode vecMode; member in class:FullO3CPU
H A Dregfile.hh136 VecMode vecMode; member in class:PhysRegFile

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