Searched refs:that (Results 1 - 25 of 44) sorted by relevance

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/gem5/src/cpu/
H A Dinst_res.hh10 * terms below provided that you ensure that this notice is replicated
15 * modification, are permitted provided that the following conditions are
97 InstResult& operator=(const InstResult& that) { argument
98 type = that.type;
100 /* Given that misc regs are not written to, there may be invalids in
105 result.integer = that.result.integer;
108 result.vecElem = that.result.vecElem;
111 result.vector = that.result.vector;
114 result.pred = that
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H A Dreg_class.hh10 * terms below provided that you ensure that this notice is replicated
18 * modification, are permitted provided that the following conditions are
108 bool operator==(const RegId& that) const {
109 return regClass == that.classValue() && regIdx == that.index()
110 && elemIdx == that.elemIndex();
113 bool operator!=(const RegId& that) const {
114 return !(*this==that);
120 bool operator<(const RegId& that) cons
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/gem5/src/systemc/tests/tlm/multi_sockets/
H A DextensionPool.h28 that=content;
31 T* that; member in struct:ExtensionPool::entry
38 mine.push_back(unused->that);
43 mine.push_back(unused->that);
48 //delete all T* that belong to this pool
79 mine.push_back(e->that);
87 return used->that; //if all elements of pool are used, just create a new one and go on
94 e->that=cont;
/gem5/ext/systemc/src/sysc/kernel/
H A Dsc_except.h105 sc_unwind_exception::sc_unwind_exception( const sc_unwind_exception& that )
106 : std::exception( that )
107 , m_proc_p( that.m_proc_p )
108 , m_is_reset( that.m_is_reset )
110 that.m_proc_p = 0; // move to new instance
H A Dsc_event.h331 extern sc_event sc_non_event; // Event that never happens.
496 sc_event_list::sc_event_list( sc_event_list const & that )
498 , m_and_list( that.m_and_list )
502 move_from( that );
503 that.auto_delete(); // free automatic lists
508 sc_event_list::operator=( sc_event_list const & that )
513 move_from( that );
514 that.auto_delete(); // free automatic lists
528 sc_event_list::swap( sc_event_list& that )
530 if( busy() || that
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64mi/
H A Dmcsr.S16 # Check that mcpuid reports the correct XLEN
23 # Check that mhartid reports 0
26 # Check that reading the following CSRs doesn't cause an exception
31 # Check that writing hte following CSRs doesn't cause an exception
/gem5/src/arch/generic/
H A Dvec_pred_reg.hh9 // terms below provided that you ensure that this notice is replicated
14 // modification, are permitted provided that the following conditions are
105 operator=(const MyClass& that) argument
107 container = that.container;
145 operator==(const VecPredRegT<VE2, NE2, P2, C2>& that) const
147 return container == that.container;
153 operator!=(const VecPredRegT<VE2, NE2, P2, C2>& that) const
155 return !operator==(that);
253 operator=(const MyClass& that) argument
263 operator =(const std::vector<uint8_t>& that) argument
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H A Dvec_reg.hh10 * terms below provided that you ensure that this notice is replicated
15 * modification, are permitted provided that the following conditions are
46 * It takes into account the possibility that different architectural names
49 * The design is having a basic vector register container that holds the
54 * This file also describes two views of the container that have semantic
58 * elements that the vector contains (NumElems). The size of a view,
88 * // template parametre, the second has a default value that works, and the
107 * // Usage example, for a micro op that operates over lane number _lidx:
122 * // As this is a partial write, we need the exec context to support that
200 operator =(const MyClass& that) argument
288 VecRegContainer(const std::vector<uint8_t>& that) argument
300 operator =(const MyClass& that) argument
309 operator =(const Container& that) argument
318 operator =(const std::vector<uint8_t>& that) argument
481 operator =(const T& that) argument
554 operator =(const VecElem& that) argument
565 operator =(const T& that) argument
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/gem5/src/base/
H A Dcircular_queue.hh10 * terms below provided that you ensure that this notice is replicated
15 * modification, are permitted provided that the following conditions are
68 * an element of the vector that is out-of-bounds of the circular queue,
69 * while 'o' represents and element that is inside the bounds. The
70 * characters '[' and ']' are added to mark the entries that hold the head
98 * ambiguity, we need the round number to guarantee that it did not become
138 * iterator implementation to provide the circular-ness that the
196 * index is a valid index to that queue. PTE test is required to
220 bool operator==(const iterator& that) cons
230 operator !=(const iterator& that) argument
369 operator -(const iterator& that) argument
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/gem5/src/mem/cache/prefetch/
H A Dqueued.hh10 * terms below provided that you ensure that this notice is replicated
15 * modification, are permitted provided that the following conditions are
86 bool operator>(const DeferredPacket& that) const
88 return priority > that.priority;
90 bool operator<(const DeferredPacket& that) const
92 return priority < that.priority;
94 bool operator<=(const DeferredPacket& that) const
96 return !(*this > that);
103 * @param mid Requester ID of the access that generate
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/gem5/ext/systemc/src/sysc/utils/
H A Dsc_report.cpp130 sc_report::swap( sc_report & that )
133 swap( severity, that.severity );
134 swap( md, that.md );
135 swap( msg, that.msg );
136 swap( file, that.file );
137 swap( line, that.line );
138 swap( timestamp, that.timestamp );
139 swap( process, that.process );
140 swap( m_verbosity_level, that.m_verbosity_level );
141 swap( m_what, that
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H A Dsc_vector.h305 bool operator== ( const this_type& that ) const { return it_ == that.it_; }
306 bool operator!= ( const this_type& that ) const { return it_ != that.it_; }
307 bool operator<= ( const this_type& that ) const { return it_ <= that.it_; }
308 bool operator>= ( const this_type& that ) const { return it_ >= that.it_; }
309 bool operator< ( const this_type& that ) const { return it_ < that
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ui/
H A Dsimple.S8 # pass thiss then there is little chance that it will pass any of the
H A Dsll.S38 # Verify that shifts only use bottom six bits
H A Dsllw.S38 # Verify that shifts only use bottom five bits
H A Dsra.S38 # Verify that shifts only use bottom five bits
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64uf/
H A Dldst.S7 # This test verifies that flw, fld, fsw, and fsd work properly.
H A Dmove.S7 # This test verifies that the fmv.s.x, fmv.x.s, and fsgnj[x|n].d instructions
/gem5/src/dev/arm/
H A DFlashDevice.py9 # terms below provided that you ensure that this notice is replicated
14 # modification, are permitted provided that the following conditions are
62 that the GC is activated if a block is full")
/gem5/src/cpu/kvm/
H A Dperfevent.hh10 * terms below provided that you ensure that this notice is replicated
15 * modification, are permitted provided that the following conditions are
94 * Set the number of samples that need to be triggered before
304 PerfKvmCounter(const PerfKvmCounter &that);
306 PerfKvmCounter &operator=(const PerfKvmCounter &that);
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/
H A Dma_fetch.S128 # verify that return address was not written
136 # verify that epc == &jalr (== t0 - 4)
141 # verify that badaddr == 0 or badaddr == t0+2.
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ua/
H A Dlrsc.S28 # make sure that sc without a reservation fails.
34 # make sure that sc with the wrong reservation fails.
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ud/
H A Dldst.S7 # This test verifies that flw, fld, fsw, and fsd work properly.
H A Dstructural.S7 # This test verifies that the FPU correctly obviates structural hazards on its
/gem5/src/systemc/dt/int/
H A Dsc_nbcommon.inc29 of the class that they interface to.
779 // Note that u = q * v + r for r < q.
903 // Note that u = q * v + r for r < q.
1227 // Note that u ^ v = (~u &v) | (u & ~v).
2079 // that the number has infinite length.
2311 // make sure that l and r point to the bits of u
2342 // The indices of the digits that have lth and rth bits, respectively.
2349 // first get the indices for that.
2450 // make sure that l and r point to the bits of u
2481 // The indices of the digits that hav
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