Searched refs:store_inst (Results 1 - 7 of 7) sorted by relevance

/gem5/src/cpu/o3/
H A Dlsq_unit_impl.hh316 LSQUnit<Impl>::insertStore(const DynInstPtr& store_inst) argument
323 store_inst->pcState(), storeQueue.tail(), store_inst->seqNum);
326 store_inst->sqIdx = storeQueue.tail();
327 store_inst->lqIdx = loadQueue.moduloAdd(loadQueue.tail(), 1);
328 store_inst->lqIt = loadQueue.end();
330 storeQueue.back().set(store_inst);
600 LSQUnit<Impl>::executeStore(const DynInstPtr &store_inst) argument
606 int store_idx = store_inst->sqIdx;
609 store_inst
1005 DynInstPtr store_inst = store_idx->instruction(); local
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H A Dmem_dep_unit.hh158 void violation(const DynInstPtr &store_inst,
H A Dmem_dep_unit_impl.hh540 MemDepUnit<MemDepPred, Impl>::violation(const DynInstPtr &store_inst, argument
545 store_inst->instAddr());
547 depPred.violation(store_inst->instAddr(), violating_load->instAddr());
H A Dlsq_impl.hh241 LSQ<Impl>::insertStore(const DynInstPtr &store_inst)
243 ThreadID tid = store_inst->threadNumber;
245 thread[tid].insertStore(store_inst);
H A Dlsq_unit.hh250 void insertStore(const DynInstPtr &store_inst);
H A Dlsq.hh847 void insertStore(const DynInstPtr &store_inst);
/gem5/tests/test-progs/asmtest/src/riscv/isa/macros/scalar/
H A Dtest_macros.h224 #define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
228 store_inst x2, offset(x1); \
259 #define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
267 store_inst x1, offset(x2); \
275 #define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
283 store_inst x1, offset(x2); \

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