Searched refs:src0 (Results 1 - 1 of 1) sorted by relevance

/gem5/src/arch/hsail/insts/
H A Ddecl.hh227 typename Src0OperandType::SrcOperand src0; member in class:HsailISA::ThreeNonUniformSourceInstBase
235 src0.disassemble(), src1.disassemble(),
251 src0.init(op_offs, obj);
263 return src0.isVectorRegister();
274 return src0.isCondRegister();
285 return src0.isScalarRegister();
310 return src0.opSize();
324 return src0.regIndex();
335 if (src0.isVectorRegister()) {
408 typename Src0OperandType::SrcOperand src0; member in class:HsailISA::TwoNonUniformSourceInstBase
537 fpclassify(T src0, uint32_t src1) argument
592 compare(T src0, T src1, Brig::BrigCompareOperation cmpOp) argument
648 firstbit(T src0) argument
880 ImmOperand<SrcCType> src0; member in class:HsailISA::SpecialInst1SrcBase
1182 FunctionRefOperand src0; member in class:HsailISA::Call
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