/gem5/src/arch/x86/ |
H A D | utility.cc | 103 tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL); 104 tc->setMiscReg(MISCREG_CR8, 0); 108 tc->setMiscReg(MISCREG_MTRRCAP, 0x0508); 110 tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0); 111 tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0); 113 tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0); 114 tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0); 115 tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0); 116 tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0); 117 tc->setMiscReg(MISCREG_MTRR_FIX_4K_C800 [all...] |
H A D | faults.cc | 152 tc->setMiscReg(MISCREG_CR2, addr); 154 tc->setMiscReg(MISCREG_CR2, (uint32_t)addr); 198 tc->setMiscReg(MISCREG_CR0, newCR0); 199 tc->setMiscReg(MISCREG_CR2, 0); 200 tc->setMiscReg(MISCREG_CR3, 0); 201 tc->setMiscReg(MISCREG_CR4, 0); 203 tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002ULL); 205 tc->setMiscReg(MISCREG_EFER, 0); 222 tc->setMiscReg(MISCREG_SEG_SEL(seg), 0); 223 tc->setMiscReg(MISCREG_SEG_BAS [all...] |
H A D | system.cc | 100 tc->setMiscReg(MISCREG_SEG_BASE(seg), desc.base); 101 tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), honorBase ? desc.base : 0); 102 tc->setMiscReg(MISCREG_SEG_LIMIT(seg), desc.limit); 103 tc->setMiscReg(MISCREG_SEG_ATTR(seg), (RegVal)attr); 176 tc->setMiscReg(MISCREG_CS, (RegVal)cs); 188 tc->setMiscReg(MISCREG_DS, (RegVal)ds); 189 tc->setMiscReg(MISCREG_ES, (RegVal)ds); 190 tc->setMiscReg(MISCREG_FS, (RegVal)ds); 191 tc->setMiscReg(MISCREG_GS, (RegVal)ds); 192 tc->setMiscReg(MISCREG_S [all...] |
H A D | process.cc | 359 tc->setMiscReg(MISCREG_CS, cs); 360 tc->setMiscReg(MISCREG_DS, ds); 361 tc->setMiscReg(MISCREG_ES, ds); 362 tc->setMiscReg(MISCREG_FS, ds); 363 tc->setMiscReg(MISCREG_GS, ds); 364 tc->setMiscReg(MISCREG_SS, ds); 367 tc->setMiscReg(MISCREG_TSL, 0); 371 tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr); 373 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr); 374 tc->setMiscReg(MISCREG_TSG_LIMI [all...] |
H A D | pseudo_inst.cc | 57 tc->setMiscReg(MISCREG_RFLAGS, rflags);
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H A D | isa.hh | 71 void setMiscReg(int miscReg, RegVal val, ThreadContext *tc);
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H A D | mmapped_ipr.hh | 87 xc->setMiscReg(index, gtoh(data));
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/gem5/src/arch/arm/ |
H A D | isa_device.hh | 75 virtual void setMiscReg(int misc_reg, RegVal val) = 0; 103 void setMiscReg(int misc_reg, RegVal val) override;
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H A D | locked_mem.hh | 85 xc->setMiscReg(MISCREG_LOCKFLAG, false); 87 xc->setMiscReg(MISCREG_SEV_MAILBOX, true); 96 xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr()); 97 xc->setMiscReg(MISCREG_LOCKFLAG, true); 108 xc->setMiscReg(MISCREG_LOCKFLAG, false); 109 xc->setMiscReg(MISCREG_SEV_MAILBOX, true); 129 xc->setMiscReg(MISCREG_LOCKFLAG, false); 160 xc->setMiscReg(MISCREG_LOCKFLAG, false); 162 xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
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H A D | isa_device.cc | 61 DummyISADevice::setMiscReg(int misc_reg, RegVal val) function in class:ArmISA::DummyISADevice
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H A D | faults.cc | 420 tc->setMiscReg(syndrome_reg, value); 555 tc->setMiscReg(MISCREG_CPSR, cpsr); 558 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 561 tc->setMiscReg(MISCREG_LOCKFLAG, 0); 564 tc->setMiscReg(MISCREG_ELR_HYP, curPc + 573 tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr); 576 tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr); 579 tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr); 583 tc->setMiscReg(MISCREG_SPSR_MON, saved_cpsr); 586 tc->setMiscReg(MISCREG_SPSR_AB [all...] |
/gem5/src/arch/alpha/ |
H A D | locked_mem.hh | 82 xc->setMiscReg(MISCREG_LOCKFLAG, false); 90 xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf); 91 xc->setMiscReg(MISCREG_LOCKFLAG, true); 116 xc->setMiscReg(MISCREG_LOCKFLAG, false);
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H A D | isa.hh | 81 void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc,
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H A D | isa.cc | 143 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid)
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/gem5/src/arch/mips/ |
H A D | locked_mem.hh | 72 xc->setMiscReg(MISCREG_LLFLAG, false); 80 xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf); 81 xc->setMiscReg(MISCREG_LLFLAG, true); 110 xc->setMiscReg(MISCREG_LLFLAG, false);
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H A D | mt.hh | 97 return otc->setMiscReg(reg.index(), val); 144 tc->setMiscReg(MISCREG_TC_RESTART, pc.npc()); 231 tc->setMiscReg(MISCREG_VPE_CONTROL, vpeControl); 273 tc->setMiscReg(MISCREG_TC_STATUS, tcStatus); 281 tc->setMiscReg(MISCREG_VPE_CONTROL, vpeControl);
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H A D | isa.hh | 101 void setMiscReg(int misc_reg, RegVal val,
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/gem5/src/arch/riscv/ |
H A D | faults.cc | 122 tc->setMiscReg(cause, 124 tc->setMiscReg(epc, tc->instAddr()); 125 tc->setMiscReg(tval, trap_value()); 126 tc->setMiscReg(MISCREG_PRV, prv); 127 tc->setMiscReg(MISCREG_STATUS, status); 143 tc->setMiscReg(MISCREG_PRV, PRV_M); 147 tc->setMiscReg(MISCREG_STATUS, status); 148 tc->setMiscReg(MISCREG_MCAUSE, 0);
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H A D | isa.hh | 80 void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc);
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/gem5/src/arch/sparc/ |
H A D | utility.cc | 98 dest->setMiscReg(MISCREG_ASI, 122 dest->setMiscReg(MISCREG_CWP, 134 dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL)); 211 src->setMiscReg(MISCREG_GL, x); 212 dest->setMiscReg(MISCREG_GL, x); 219 src->setMiscReg(MISCREG_CWP, x); 220 dest->setMiscReg(MISCREG_CWP, x); 229 src->setMiscReg(MISCREG_GL, old_gl); 230 src->setMiscReg(MISCREG_CWP, old_cwp);
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H A D | process.cc | 141 tc->setMiscReg(MISCREG_CWP, 0); 148 tc->setMiscReg(MISCREG_ASI, ASI_PRIMARY); 151 tc->setMiscReg(MISCREG_MMU_P_CONTEXT, _pid); 170 tc->setMiscReg(MISCREG_PSTATE, pstate); 184 tc->setMiscReg(MISCREG_PSTATE, pstate); 448 tc->setMiscReg(MISCREG_CWP, CWP); 467 tc->setMiscReg(MISCREG_CWP, origCWP); 483 tc->setMiscReg(MISCREG_CWP, CWP); 502 tc->setMiscReg(MISCREG_CWP, origCWP);
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H A D | ua2005.cc | 104 return setMiscReg(MISCREG_SOFTINT, ~val & softint, tc); 106 return setMiscReg(MISCREG_SOFTINT, val | softint, tc); 343 setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); 370 setMiscReg(MISCREG_HINTP, 1, tc);
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H A D | faults.cc | 289 tc->setMiscReg(MISCREG_HPSTATE, hpstate); 294 tc->setMiscReg(MISCREG_PSTATE, pstate); 346 tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL)); 372 tc->setMiscReg(MISCREG_CWP, CWP); 430 tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxPGL)); 432 tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxGL)); 468 tc->setMiscReg(MISCREG_CWP, CWP); 569 tc->setMiscReg(MISCREG_GL, MaxGL); 726 // XXX: Inspecting how setMiscReg and setMiscRegNoEffect behave for
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/gem5/src/arch/power/ |
H A D | isa.hh | 85 setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) function in class:PowerISA::ISA
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/gem5/src/cpu/o3/ |
H A D | dyn_inst.hh | 149 setMiscReg(int misc_reg, RegVal val) override 189 setMiscReg(reg.index(), val); 204 this->cpu->setMiscReg(
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