arch/x86/process.cc

359             tc->setMiscReg(MISCREG_CS, cs);
360             tc->setMiscReg(MISCREG_DS, ds);
361             tc->setMiscReg(MISCREG_ES, ds);
362             tc->setMiscReg(MISCREG_FS, ds);
363             tc->setMiscReg(MISCREG_GS, ds);
364             tc->setMiscReg(MISCREG_SS, ds);
367             tc->setMiscReg(MISCREG_TSL, 0);
371             tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
373             tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
374             tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
376             tc->setMiscReg(MISCREG_TR, tssSel);
377             tc->setMiscReg(MISCREG_TR_BASE, tss_base_addr);
378             tc->setMiscReg(MISCREG_TR_EFF_BASE, 0);
379             tc->setMiscReg(MISCREG_TR_LIMIT, tss_limit);
380             tc->setMiscReg(MISCREG_TR_ATTR, tss_attr);
397             tc->setMiscReg(MISCREG_EFER, efer);
414             tc->setMiscReg(MISCREG_CR0, cr0);
417             tc->setMiscReg(MISCREG_CR2, cr2);
420             tc->setMiscReg(MISCREG_CR3, cr3);
437             tc->setMiscReg(MISCREG_CR4, cr4);
440             tc->setMiscReg(MISCREG_CR8, cr8);
442             tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
444             tc->setMiscReg(MISCREG_APIC_BASE, 0xfee00900);
446             tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
447             tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
449             tc->setMiscReg(MISCREG_IDTR_BASE, IDTVirtAddr);
450             tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
454             tc->setMiscReg(MISCREG_STAR, star);
456             tc->setMiscReg(MISCREG_LSTAR, lstar);
458             tc->setMiscReg(MISCREG_SF_MASK, sfmask);
614             tc->setMiscReg(MISCREG_EFER, efer);
631             tc->setMiscReg(MISCREG_CR0, cr0);
633             tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
734         tc->setMiscReg(MISCREG_EFER, efer);
751         tc->setMiscReg(MISCREG_CR0, cr0);
753         tc->setMiscReg(MISCREG_MXCSR, 0x1f80);