Searched refs:rip (Results 1 - 9 of 9) sorted by relevance

/gem5/src/arch/x86/
H A Dnativetrace.cc63 rip = X86ISA::gtoh(rip);
90 rip = tc->pcState().npc();
172 checkReg("rip", mState.rip, nState.rip);
H A Dnativetrace.hh66 uint64_t rip; member in struct:Trace::X86NativeTrace::ThreadState
H A Dremote_gdb.hh116 uint64_t rip; member in struct:X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
H A Dremote_gdb.cc127 r.rip = context->pcState().pc();
179 context->pcState(r.rip);
/gem5/util/statetrace/arch/amd64/
H A Dtracechild.cc117 case RIP: return myregs.rip;
324 uint64_t rip = getPC(); local
328 uint64_t buf = ptrace(PTRACE_PEEKDATA, pid, rip, 0);
352 return rip + 1;
358 return rip + 1;
360 return rip + 2;
368 rip++;
382 //instruction, leaving the rip where it should be, or it will take
383 //over after this instruction, -still- leaving the rip where it should
/gem5/util/m5/
H A Dm5op_x86.S41 mov m5_mem@gotpcrel(%rip), %r11; \
/gem5/src/arch/x86/insts/
H A Dstatic_inst.hh105 uint64_t disp, uint8_t addressSize, bool rip) const;
H A Dstatic_inst.cc233 uint64_t disp, uint8_t addressSize, bool rip) const
238 if (rip) {
239 os << "rip";
/gem5/src/cpu/kvm/
H A Dx86_cpu.cc181 inform("\trip: 0x%llx\n", regs.rip);
696 regs.rip = tc->instAddr() - tc->readMiscReg(MISCREG_CS_BASE);
981 tc->pcState(PCState(regs.rip + sregs.cs.base));

Completed in 10 milliseconds