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Searched refs:rd (Results 1 - 21 of 21) sorted by relevance

/gem5/tests/test-progs/insttest/src/riscv/
H A D	rv64i.h	44 int64_t rd = -1; local 45 asm volatile("lui %0,%1" : "=r" (rd) : "i" (imm)); 46 return rd; 52 int64_t rd = -1; local 53 asm volatile("auipc %0,%1" : "=r" (rd) : "i" (imm)); 54 std::cout << "auipc: 0x" << std::hex << std::uppercase << rd << 56 return rd >= imm; 219 int64_t rd = 0; local 220 IOP("addi", rd, rs1, imm); 221 return rd; 227 bool rd = false; local 235 bool rd = false; local 243 uint64_t rd = 0; local 251 uint64_t rd = 0; local 259 uint64_t rd = 0; local 267 int64_t rd = 0; local 275 uint64_t rd = 0; local 283 int64_t rd = 0; local 291 int64_t rd = 0; local 299 int64_t rd = 0; local 307 int64_t rd = 0; local 315 bool rd = false; local 323 bool rd = false; local 331 uint64_t rd = 0; local 339 uint64_t rd = 0; local 347 int64_t rd = 0; local 355 uint64_t rd = 0; local 363 uint64_t rd = 0; local 371 int64_t rd = 0; local 379 int64_t rd = 0; local 387 uint64_t rd = 0; local 395 int64_t rd = 0; local 403 int64_t rd = 0; local 411 int64_t rd = 0; local 419 int64_t rd = 0; local 427 uint64_t rd = 0; local 435 int64_t rd = 0; local [all...]
H A D	rv64m.h	`43 int64_t rd = 0; local 44 ROP("mul", rd, rs1, rs2); 45 return rd; 51 int64_t rd = 0; local 52 ROP("mulh", rd, rs1, rs2); 53 return rd; 59 int64_t rd = 0; local 60 ROP("mulhsu", rd, rs1, rs2); 61 return rd; 67 uint64_t rd local 75 int64_t rd = 0; local 83 uint64_t rd = 0; local 91 int64_t rd = 0; local 99 uint64_t rd = 0; local 107 int64_t rd = 0; local 115 int64_t rd = 0; local 123 uint64_t rd = 0; local 131 int64_t rd = 0; local 139 uint64_t rd = 0; local [all...]`
H A D	rv64a.h	54 uint64_t rd = -1; local 56 : "=r" (rd) 59 return {mem, rd}; 65 int64_t rd = 0; local 68 : "=r" (rd) 71 return {mem, rd}; 77 int64_t rd = 0; local 80 : "=r" (rd) 83 return {mem, rd}; 89 uint64_t rd local 101 uint64_t rd = 0; local 113 uint64_t rd = 0; local 125 int64_t rd = 0; local 137 int64_t rd = 0; local 149 uint64_t rd = 0; local 161 uint64_t rd = 0; local 183 uint64_t rd = -1; local 194 int64_t rd = 0; local 206 int64_t rd = 0; local 218 uint64_t rd = 0; local 230 uint64_t rd = 0; local 242 uint64_t rd = 0; local 254 int64_t rd = 0; local 266 int64_t rd = 0; local 278 uint64_t rd = 0; local 290 uint64_t rd = 0; local [all...]
H A D	rv64c.h	39 #define CROP(op, rd, rs) asm volatile(op " %0,%1" : "+r" (rd) : "r" (rs)) 47 int64_t rd = 0; local 48 CIOP("c.li", rd, imm); 49 return rd; 55 int64_t rd = 0; local 56 CIOP("c.lui", rd, imm); 57 return rd; 77 uint64_t rd = 0; local 78 asm volatile("c.addi4spn %0,sp,%1" : "=r" (rd) 113 int64_t rd = 0; local 119 c_add(int64_t rd, int64_t rs) argument 126 c_and(int64_t rd, int64_t rs) argument 133 c_or(int64_t rd, int64_t rs) argument 140 c_xor(int64_t rd, int64_t rs) argument 147 c_sub(int64_t rd, int64_t rs) argument 154 c_addw(int64_t rd, int64_t rs) argument 161 c_subw(int64_t rd, int64_t rs) argument [all...]
H A D	rv64f.h	86 uint64_t rd = -1; local 87 asm volatile("frflags %0" : "=r" (rd)); 88 return rd; 94 uint64_t rd = -1; local 95 asm volatile("fsflags %0,%1" : "=r" (rd) : "r" (rs1)); 96 return rd; 215 int64_t rd = 0; local 216 asm volatile("fcvt.w.s %0,%1" : "=r" (rd) : "f" (fs1)); 217 return rd; 223 uint64_t rd local 231 uint64_t rd = 0; local 239 bool rd = false; local 247 bool rd = false; local 255 bool rd = false; local 263 uint64_t rd = -1; local 295 uint64_t rd = -1; local 303 uint64_t rd = -1; local 311 uint64_t rd = -1; local 319 uint64_t rd = -1; local 327 int64_t rd = 0; local 336 int64_t rd = 0; local [all...]
H A D	rv64d.h	214 bool rd = false; local 215 asm volatile("feq.d %0,%1,%2" : "=r" (rd) : "f" (fs1), "f" (fs2)); 216 return rd; 222 bool rd = false; local 223 asm volatile("flt.d %0,%1,%2" : "=r" (rd) : "f" (fs1), "f" (fs2)); 224 return rd; 230 bool rd = false; local 231 asm volatile("fle.d %0,%1,%2" : "=r" (rd) : "f" (fs1), "f" (fs2)); 232 return rd; 238 uint64_t rd local 246 int64_t rd = 0; local 254 uint64_t rd = 0; local 278 int64_t rd = 0; local 286 uint64_t rd = 0; local 294 uint64_t rd = 0; local [all...]
H A D	insttest.h	`39 #define IOP(inst, rd, rs1, imm) \ 40 asm volatile(inst " %0,%1,%2" : "=r" (rd) : "r" (rs1), "i" (imm)) 42 #define ROP(inst, rd, rs1, rs2) \ 43 asm volatile(inst " %0,%1,%2" : "=r" (rd) : "r" (rs1), "r" (rs2))`
H A D	rv64c.cpp	`166 uint64_t sp = 0, rd = 0; 172 : "+r" (sp), "=r" (rd) 174 return rd == sp + i16; 179 uint64_t sp = 0, rd = 0; 183 : "=r" (sp), "=r" (rd) 185 return rd == sp + i4;`
H A D	rv64a.cpp	`46 int64_t rd; 49 rd = A::lr_w(mem); 52 return pair<int64_t, uint64_t>(rd, result.first); 140 int64_t rd; 143 rd = A::lr_d(mem); 146 return pair<int64_t, uint64_t>(rd, result.first);`
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ud/
H A D	move.S	`42 #define TEST_FSGNJS(n, rd, rs1, rs2) \ 43 TEST_CASE(n, a0, (rd) \| (-((rd) >> 31) << 32), \ 50 TEST_CASE(1##n, a0, (rd) \| 0xffffffff00000000, \ 74 #define TEST_FSGNJD_SP(n, isnan, rd, rs1, rs2) \ 75 TEST_CASE(n, a0, ((rd) & 0xffffffff) \| (-(((rd) >> 31) & 1) << 32), \ 86 TEST_CASE(1##n, a0, rd, \`
/gem5/ext/mcpat/cacti/
H A D	decoder.cc	183 double rd, tf, this_delay, c_load, c_intrinsic, Vpp; local 195 rd = tr_R_on(w_dec_n[0], NCH, num_in_signals, is_dram, false, is_wl_tr); 199 tf = rd * (c_intrinsic + c_load); 206 rd = tr_R_on(w_dec_n[i], NCH, 1, is_dram, false, is_wl_tr); 210 tf = rd * (c_intrinsic + c_load); 220 rd = tr_R_on(w_dec_n[i], NCH, 1, is_dram, false, is_wl_tr); 223 tf = rd * (c_intrinsic + c_load) + R_wire_dec_out * c_load / 2; 665 double rd, c_load, c_intrinsic, tf, this_delay; local 675 rd = tr_R_on(w_L1_nand2_n[0], NCH, 2, is_dram_); 679 tf = rd * (c_intrinsi 1189 double rd, c_gate_load, c_load, c_intrinsic, tf, this_delay; local 1456 double rd, c_load, c_intrinsic, tf; local [all...]
H A D	mat.cc	479 double rd, C_intrinsic, C_ld, tf, R_bl_precharge, r_b_metal, R_bl, C_bl; local 488 rd = tr_R_on(ml_to_ram_wl_drv->width_n[k], NCH, 1, is_dram, false, true); 495 tf = rd * (C_intrinsic + C_ld) + ml_to_ram_wl_drv->r_wire_load * C_ld / 2; 539 double rd = tr_R_on(row_dec->w_dec_n[k], NCH, 1, is_dram, false, true); local 546 double tf = rd * (C_intrinsic + C_ld) + row_dec->R_wire_dec_out * C_ld / 2; 656 double Rwire, tf, c_intrinsic, rd, Cwire, c_gate_load; local 819 rd = tr_R_on(Wdummyn, NCH, 2, is_dram); 839 tf = rd * (c_intrinsic + Cwire / 2 + c_gate_load) + Rwire * (Cwire / 2 + c_gate_load); 850 rd = tr_R_on(Waddrnandn, NCH, 2, is_dram); 854 tf = rd * (c_intrinsi 1268 double C_ld, rd, tf, this_delay; local [all...]
H A D	technology.cc	`2650 double rd = tr_R_on(g_tp.min_w_nmos_, NCH, 1); local 2653 double tf = rd * c_load; 2659 tf = rd * c_load;`
/gem5/util/m5/
H A D	m5op_sparc.S	`37 #define INST(func, rs1, rs2, rd) \ 38 .long (m5_op) << 30 \| (rd) << 25 \| (m5_op3) << 19 \| (func) << 7 \| \`
/gem5/src/systemc/tests/systemc/misc/unit/data/user_guide/ch9/std_ulogic_vector_datatype/
H A D	std_ulogic_vector_datatype.cpp	`422 std_ulogic_vector<9> rd; local 440 ( rd.range(8,6), rd.range(5,0) ) = rdata9; 465 << rd[0] << "\t" << rd[1] << "\t" << rd[2] << "\t" 466 << rd[3] << "\t" << rd[4] << "\t" << rd[5] << "\t" 467 << rd[ [all...]`
/gem5/src/arch/arm/insts/
H A D	pred_inst.cc	`55 (IntRegIndex)(uint32_t)machInst.rd, 69 (IntRegIndex)(uint32_t)machInst.rd,`
H A D	static_inst.cc	`590 bool immShift, bool s, IntRegIndex rd, IntRegIndex rn, 598 if (rd != INTREG_ZERO) { 600 printIntReg(os, rd);`
H A D	static_inst.hh	`189 IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,`
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64mi/
H A D	access.S	`23 # jalr to an illegal address should commit (hence should write rd).`
/gem5/src/arch/arm/
H A D	types.hh	`124 Bitfield<15, 12> rd; member in namespace:ArmISA`
/gem5/src/arch/x86/regs/
H A D	misc.hh	`823 Bitfield<4> rd; // RdMem Enable member in namespace:X86ISA`

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