Searched refs:pitch (Results 1 - 11 of 11) sorted by relevance

/gem5/ext/mcpat/cacti/
H A Dparameter.cc77 cout << indent_str << "pitch = " << setw(12) << pitch << " um" << endl;
321 cam_cell.h = g_tp.cam.b_h + 2 * wire_local.pitch *
323 + 2 * wire_local.pitch * (g_ip->num_search_ports - 1) +
324 wire_local.pitch * g_ip->num_se_rd_ports;
325 cam_cell.w = g_tp.cam.b_w + 2 * wire_local.pitch *
327 + 2 * wire_local.pitch * (g_ip->num_search_ports - 1) +
328 wire_local.pitch * g_ip->num_se_rd_ports;
330 cell.h = g_tp.sram.b_h + 2 * wire_local.pitch *
332 + 2 * wire_local.pitch * (g_i
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H A Dhtree2.cc311 g_tp.wire_outside_mat.pitch *
316 g_tp.wire_outside_mat.pitch *
323 g_tp.wire_outside_mat.pitch) +
325 g_tp.wire_outside_mat.pitch * h)
330 g_tp.wire_outside_mat.pitch) +
332 g_tp.wire_outside_mat.pitch * v)) / 2;
339 g_tp.wire_outside_mat.pitch) +
341 g_tp.wire_outside_mat.pitch *
346 (ndwl / 2 - 1) * g_tp.wire_outside_mat.pitch) +
348 g_tp.wire_outside_mat.pitch *
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H A Dcrossbar.cc54 double l_eff = n_inp * flit_size * g_tp.wire_outside_mat.pitch;
107 int ntri = (int)ceil(g_tp.cell_h_def / (g_tp.wire_outside_mat.pitch));
109 flit_size * g_tp.wire_outside_mat.pitch * n_out);
113 area.h = g_tp.wire_outside_mat.pitch * n_inp * flit_size * CB_ADJ;
153 double l_eff = n_inp * flit_size * g_tp.wire_outside_mat.pitch;
H A Dparameter.h104 double pitch; member in class:TechnologyParameter::InterconnectType
113 InterconnectType(): pitch(0), R_per_um(0), C_per_um(0) { };
116 pitch = 0;
H A Dsubarray.cc79 + 16 * g_tp.wire_local.pitch
81 + 128 * g_tp.wire_local.pitch;
167 C_wl += (16 + 128) * g_tp.wire_local.pitch *
171 R_wl += (16 + 128) * g_tp.wire_local.pitch *
H A Drouter.cc188 dyn_p.cell.h = g_tp.sram.b_h + 2 * g_tp.wire_outside_mat.pitch * (dyn_p.num_wr_ports +
190 dyn_p.cell.w = g_tp.sram.b_w + 2 * g_tp.wire_outside_mat.pitch * (dyn_p.num_rw_ports - 1 +
192 dyn_p.num_wr_ports) + g_tp.wire_outside_mat.pitch * dyn_p.num_se_rd_ports;
H A Dwire.cc95 wire_width = g_tp.wire_outside_mat.pitch;
98 wire_width = g_tp.wire_inside_mat.pitch;
101 wire_width = g_tp.wire_local.pitch;
131 wire_width = g_tp.wire_outside_mat.pitch;
133 wire_width = g_tp.wire_inside_mat.pitch;
135 wire_width = g_tp.wire_local.pitch;
H A Dmat.cc324 g_tp.wire_inside_mat.pitch * (RWP + ERP + EWP);
334 h_bit_mux_dec_out_wires = deg_bl_muxing * g_tp.wire_inside_mat.pitch * (RWP + ERP);
337 h_senseamp_mux_dec_out_wires = dp.Ndsam_lev_1 * g_tp.wire_inside_mat.pitch * (RWP + ERP);
340 h_senseamp_mux_dec_out_wires += dp.Ndsam_lev_2 * g_tp.wire_inside_mat.pitch * (RWP + ERP);
349 g_tp.wire_inside_mat.pitch * (RWP + ERP + EWP);
356 g_tp.wire_inside_mat.pitch * (RWP + ERP + EWP) +
358 g_tp.wire_inside_mat.pitch * SCHP;
614 // height += deg_bl_muxing * g_tp.wire_inside_mat.pitch * (RWP + ERP); // bit mux dec out wires height
639 //height_write_mux_decode_output_wires = deg_bl_muxing * Ndsam * g_tp.wire_inside_mat.pitch * (RWP + EWP);
H A Dtechnology.cc1020 //For 2013, MPU/ASIC stagger-contacted M1 half-pitch is 32 nm (so this is 32 nm
1271 //For 2016, MPU/ASIC stagger-contacted M1 half-pitch is 22 nm (so this is 22 nm
1487 //For 2019, MPU/ASIC stagger-contacted M1 half-pitch is 16 nm (so this is 16 nm
2578 g_tp.wire_local.pitch += curr_alpha *
2603 g_tp.wire_inside_mat.pitch += curr_alpha *
2622 g_tp.wire_outside_mat.pitch += curr_alpha *
/gem5/util/minorview/
H A Dblobs.py243 cr.scale(*view.pitch.to_pair())
275 cr.set_line_width(view.midLineWidth / view.pitch.x)
368 cr.scale(*view.pitch.to_pair())
376 cr.set_line_width(view.midLineWidth / view.pitch.x)
385 cr.set_line_width(view.thinLineWidth / view.pitch.x)
429 cr.scale(*view.pitch.to_pair())
H A Dview.py56 # size pitch.
58 self.pitch = Point(60.0, 60.0)
65 # The scale from the units of pitch to device units (nominally
92 self.blobIndent = (self.pitch - self.blobSize).scale(0.5)
93 self.blobIndentFactor = self.blobIndent / self.pitch
177 the blob pitch"""
178 return (self.origin + self.pitch *

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