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Searched refs:phys_reg (Results 1 - 6 of 6) sorted by relevance

/gem5/src/cpu/o3/
H A D	scoreboard.hh	`81 bool getReg(PhysRegIdPtr phys_reg) const 83 assert(phys_reg->flatIndex() < numPhysRegs); 85 if (phys_reg->isFixedMapping()) { 90 bool ready = regScoreBoard[phys_reg->flatIndex()]; 92 if (phys_reg->isZeroReg()) 99 void setReg(PhysRegIdPtr phys_reg) argument 101 assert(phys_reg->flatIndex() < numPhysRegs); 103 if (phys_reg->isFixedMapping()) { 110 phys_reg->index(), phys_reg 116 unsetReg(PhysRegIdPtr phys_reg) argument [all...]`
H A D	regfile.hh	185 readIntReg(PhysRegIdPtr phys_reg) const 187 assert(phys_reg->isIntPhysReg()); 190 "%#x\n", phys_reg->index(), intRegFile[phys_reg->index()]); 191 return intRegFile[phys_reg->index()]; 195 readFloatReg(PhysRegIdPtr phys_reg) const 197 assert(phys_reg->isFloatPhysReg()); 199 RegVal floatRegBits = floatRegFile[phys_reg->index()]; 202 "has data %#x\n", phys_reg->index(), floatRegBits); 209 readVecReg(PhysRegIdPtr phys_reg) cons 222 getWritableVecReg(PhysRegIdPtr phys_reg) argument 247 setVecLane(PhysRegIdPtr phys_reg, const LD& val) argument 284 getWritableVecPredReg(PhysRegIdPtr phys_reg) argument 292 readCCReg(PhysRegIdPtr phys_reg) argument 305 setIntReg(PhysRegIdPtr phys_reg, RegVal val) argument 317 setFloatReg(PhysRegIdPtr phys_reg, RegVal val) argument 330 setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val) argument 342 setVecElem(PhysRegIdPtr phys_reg, const VecElem val) argument 354 setVecPredReg(PhysRegIdPtr phys_reg, const VecPredRegContainer& val) argument 366 setCCReg(PhysRegIdPtr phys_reg, RegVal val) argument [all...]
H A D	regfile.cc	`78 PhysRegIndex phys_reg; local 88 for (phys_reg = 0; phys_reg < numPhysicalIntRegs; phys_reg++) { 89 intRegIds.emplace_back(IntRegClass, phys_reg, flat_reg_idx++); 94 for (phys_reg = 0; phys_reg < numPhysicalFloatRegs; phys_reg++) { 95 floatRegIds.emplace_back(FloatRegClass, phys_reg, flat_reg_idx++); 100 for (phys_reg [all...]`
H A D	rename_map.hh	`137 * @param phys_reg The physical register to remap it to. 139 void setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg) argument 142 map[arch_reg.flatIndex()] = phys_reg; 249 PhysRegIdPtr phys_reg = lookup(arch_reg); local 252 return RenameInfo(phys_reg, phys_reg); 308 * @param phys_reg The physical register to remap it to. 310 void setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg) argument 314 assert(phys_reg->isIntPhysReg()); 315 return intMap.setEntry(arch_reg, phys_reg); [all...]`
H A D	cpu.cc	247 PhysRegIdPtr phys_reg = freeList.getIntReg(); local 248 renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg); local 249 commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg); local 253 PhysRegIdPtr phys_reg = freeList.getFloatReg(); local 254 renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg); local 256 RegId(FloatRegClass, ridx), phys_reg); local 266 PhysRegIdPtr phys_reg = freeList.getVecReg(); local 267 renameMap[tid].setEntry(rid, phys_reg); 268 commitRenameMap[tid].setEntry(rid, phys_reg); 284 PhysRegIdPtr phys_reg local 285 renameMap[tid].setEntry(RegId(VecPredRegClass, ridx), phys_reg); local 287 RegId(VecPredRegClass, ridx), phys_reg); local 291 PhysRegIdPtr phys_reg = freeList.getCCReg(); local 292 renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg); local 293 commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg); local 787 PhysRegIdPtr phys_reg = freeList.getIntReg(); local 795 PhysRegIdPtr phys_reg = freeList.getFloatReg(); local 803 PhysRegIdPtr phys_reg = freeList.getCCReg(); local 1199 readIntReg(PhysRegIdPtr phys_reg) argument 1207 readFloatReg(PhysRegIdPtr phys_reg) argument 1259 readCCReg(PhysRegIdPtr phys_reg) argument 1267 setIntReg(PhysRegIdPtr phys_reg, RegVal val) argument 1275 setFloatReg(PhysRegIdPtr phys_reg, RegVal val) argument 1283 setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val) argument 1291 setVecElem(PhysRegIdPtr phys_reg, const VecElem& val) argument 1299 setVecPredReg(PhysRegIdPtr phys_reg, const VecPredRegContainer& val) argument 1308 setCCReg(PhysRegIdPtr phys_reg, RegVal val) argument 1319 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( local 1330 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( local 1341 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( variable 1351 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( variable 1361 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( variable 1371 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( variable 1381 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( variable 1391 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( local 1402 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( local 1413 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( local 1424 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( local 1434 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( local 1444 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( local 1454 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( local [all...]
H A D	cpu.hh	355 RegVal readIntReg(PhysRegIdPtr phys_reg); 357 RegVal readFloatReg(PhysRegIdPtr phys_reg); 378 readVecLane(PhysRegIdPtr phys_reg) const 381 return regFile.readVecLane<VecElem, LaneIdx>(phys_reg); 389 readVecLane(PhysRegIdPtr phys_reg) const 392 return regFile.readVecLane<VecElem>(phys_reg); 398 setVecLane(PhysRegIdPtr phys_reg, const LD& val) argument 401 return regFile.setVecLane(phys_reg, val); 410 RegVal readCCReg(PhysRegIdPtr phys_reg); 412 void setIntReg(PhysRegIdPtr phys_reg, RegVa 437 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( local 448 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( local [all...]

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