Searched refs:numSrcRegOperands (Results 1 - 7 of 7) sorted by relevance

/gem5/src/arch/hsail/insts/
H A Dbranch.hh147 int numSrcRegOperands() { return 0; } function in class:HsailISA::BrnDirectInst
158 int numSrcRegOperands() { return target.isVectorRegister(); } function in class:HsailISA::BrnIndirectInst
313 int numSrcRegOperands() { return 0; } function in class:HsailISA::CbrDirectInst
327 int numSrcRegOperands() { return target.isVectorRegister(); } function in class:HsailISA::CbrIndirectInst
422 int numSrcRegOperands() { return 0; } function in class:HsailISA::BrDirectInst
433 int numSrcRegOperands() { return target.isVectorRegister(); } function in class:HsailISA::BrIndirectInst
H A Ddecl.hh191 int numSrcRegOperands() { function in class:HsailISA::CommonInstBase
333 int numSrcRegOperands() { function in class:HsailISA::ThreeNonUniformSourceInstBase
498 int numSrcRegOperands() { function in class:HsailISA::TwoNonUniformSourceInstBase
775 int numSrcRegOperands() override { return 0; }
802 int numSrcRegOperands() override { return 0; }
853 int numSrcRegOperands() { return 0; } function in class:HsailISA::SpecialInstNoSrcBase
928 int numSrcRegOperands() { return 0; } function in class:HsailISA::SpecialInst1SrcBase
1268 int numSrcRegOperands() { return 0; } function in class:HsailISA::Call
H A Dmem.hh110 int numSrcRegOperands() override
335 int numSrcRegOperands() override
901 int numSrcRegOperands() override
1366 int numSrcRegOperands() function in class:HsailISA::AtomicInstBase
/gem5/src/gpu-compute/
H A Dgpu_dyn_inst.cc76 GPUDynInst::numSrcRegOperands() function in class:GPUDynInst
78 return _staticInst->numSrcRegOperands();
H A Dgpu_static_inst.hh91 virtual int numSrcRegOperands() = 0;
300 int numSrcRegOperands() override { return 0; }
H A Dgpu_dyn_inst.hh204 int numSrcRegOperands();
H A Dwavefront.cc666 srcRegOpDist.sample(ii->numSrcRegOperands());

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