Searched refs:nsacr (Results 1 - 5 of 5) sorted by relevance

/gem5/src/arch/arm/insts/
H A Dstatic_inst.hh203 cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, argument
244 if (!isSecure && newMode == MODE_FIQ && nsacr.rfr == '1')
422 NSACR nsacr, FPEXC fpexc,
H A Dstatic_inst.cc700 NSACR nsacr, FPEXC fpexc,
715 if (nsacr.nsasedis)
717 if (nsacr.cp10 == 0)
744 if (nsacr.nsasedis)
746 if (nsacr.cp10)
/gem5/src/arch/arm/
H A Dutility.cc701 CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
796 ok &= (mode != MODE_FIQ) || !nsacr.rfr;
805 ok &= (mode != MODE_FIQ) || !nsacr.rfr;
700 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx, CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity) argument
H A Dutility.hh355 CPSR cpsr, SCR scr, NSACR nsacr,
H A Disa.cc500 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
502 if (!nsacr.cp10) cpacrMask.cp10 = 0;
503 if (!nsacr.cp11) cpacrMask.cp11 = 0;
843 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
845 if (!nsacr.cp10) cpacrMask.cp10 = 0;
846 if (!nsacr.cp11) cpacrMask.cp11 = 0;

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