Searched refs:mode (Results 1 - 25 of 141) sorted by relevance

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/gem5/src/arch/generic/
H A Dtlb.hh79 ThreadContext *tc, Mode mode) = 0;
93 const RequestPtr &req, ThreadContext *tc, Mode mode) = 0;
96 Translation *translation, Mode mode) = 0;
98 translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode) argument
114 * @param mode Request type (read/write/execute).
118 const RequestPtr &req, ThreadContext *tc, Mode mode) const = 0;
155 const RequestPtr &req, ThreadContext *tc, Mode mode) override;
158 Translation *translation, Mode mode) override;
161 const RequestPtr &req, ThreadContext *tc, Mode mode) const override;
H A Dtlb.cc43 panic("Generic translation shouldn't be used in full system mode.\n");
56 Translation *translation, Mode mode)
59 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); local
64 Mode mode) const
55 translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) argument
H A Dtraits.hh48 /** Helper structure to get the vector register mode for a given ISA.
49 * This way we implement a default 'full' mode, and only those ISA that care
59 mode(const TheISA::PCState&) function in struct:RenameMode
63 * Compare the initial rename mode of two instances of the ISA.
64 * Result is true by definition, as the default mode is Full.
/gem5/src/systemc/tests/systemc/misc/unit/data/general/concat_port/
H A Dmain.cpp53 sc_signal<int> mode ("mode");
61 concat_port D1 ("D1", clk, a, b, mode, ready, c, d, done);
63 stimgen T1 ("T1", clk, c, d, done, a, b, mode, ready);
H A Dstimgen.cpp55 mode.write(i);
57 cout << "a = " << a << " b = " << b << " mode = " << mode << endl;
H A Dconcat_port.cpp58 switch (mode.read()) {
77 default: cout << "Error: Mode " << mode.read()
H A Dconcat_port.h53 const sc_signal<int>& mode; local
74 mode (MODE),
H A Dstimgen.h57 sc_signal<int>& mode; local
77 mode (MODE),
/gem5/ext/iostream3/
H A Dzfstream.cc11 #include <cstring> // for strcpy, strcat, strlen (mode strings)
52 std::ios_base::openmode mode)
58 if ((mode & std::ios_base::in) && (mode & std::ios_base::out))
61 // Build mode string for gzopen and check it [27.8.1.3.2]
63 if (!this->open_mode(mode, char_mode))
72 io_mode = mode;
80 std::ios_base::openmode mode)
86 if ((mode & std::ios_base::in) && (mode
51 open(const char *name, std::ios_base::openmode mode) argument
79 attach(int fd, std::ios_base::openmode mode) argument
131 open_mode(std::ios_base::openmode mode, char* c_mode) const argument
379 gzifstream(const char* name, std::ios_base::openmode mode) argument
388 gzifstream(int fd, std::ios_base::openmode mode) argument
398 open(const char* name, std::ios_base::openmode mode) argument
409 attach(int fd, std::ios_base::openmode mode) argument
434 gzofstream(const char* name, std::ios_base::openmode mode) argument
443 gzofstream(int fd, std::ios_base::openmode mode) argument
453 open(const char* name, std::ios_base::openmode mode) argument
464 attach(int fd, std::ios_base::openmode mode) argument
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H A Dzfstream.h62 * @param mode Open mode flags.
67 std::ios_base::openmode mode);
72 * @param mode Open mode flags.
77 std::ios_base::openmode mode);
88 * @brief Convert ios open mode int to mode string used by zlib.
89 * @return True if valid mode flag combination.
92 open_mode(std::ios_base::openmode mode,
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/gem5/src/cpu/
H A Dtranslation.hh75 BaseTLB::Mode mode; member in class:WholeTranslationState
84 sreqLow(NULL), sreqHigh(NULL), data(_data), res(_res), mode(_mode)
87 assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
100 mode(_mode)
103 assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
253 BaseTLB::Mode mode)
256 assert(mode == state->mode);
252 finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode) argument
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/
H A Dscall.S33 # If running in M mode, use mstatus.MPP to check existence of U mode.
34 # Otherwise, if in S mode, then U mode must exist and we don't need to check.
41 # If U mode doesn't exist, mcause should indicate ECALL from M mode.
H A Dcsr.S29 # If running in M mode, use mstatus.MPP to check existence of U mode.
30 # Otherwise, if in S mode, then U mode must exist and we don't need to check.
38 # If U mode is present, UXL should be 2 (XLEN = 64-bit)
43 # If U mode is not present, UXL should be 0
82 beqz a0, finish # if no user mode, skip the rest of these checks
99 # Make sure reading status in user mode causes an exception.
124 # catch RVTEST_PASS and kick it up to M-mode
135 # Return to user mode, bu
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/gem5/src/arch/x86/
H A Ddecoder.hh98 X86Mode mode; member in class:X86ISA::Decoder
243 mode = LongMode;
245 emi.mode.mode = mode;
246 emi.mode.submode = submode;
259 mode = (X86Mode)(uint64_t)m5Reg.mode;
261 emi.mode.mode
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H A Dtlb.hh112 Translation *translation, Mode mode,
126 const RequestPtr &req, ThreadContext *tc, Mode mode) override;
129 Translation *translation, Mode mode) override;
141 * @param mode Request type (read/write/execute).
145 Mode mode) const override;
/gem5/src/arch/arm/
H A Dtlb.hh76 * @param is_priv Access from a privileged mode (i.e., not EL0)
77 * @param mode Access type
81 BaseTLB::Mode mode,
91 * @param is_priv Access from a privileged mode (i.e., not EL0)
92 * @param mode Access type
97 Addr is_priv, BaseTLB::Mode mode,
208 * @param hyp if the lookup is done from hyp mode
235 ThreadContext *tc, Mode mode,
240 ThreadContext *tc, Mode mode,
244 Fault checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode);
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H A Dutility.cc72 panic("getArgument() only implemented for full system mode.\n");
151 auto src_mode = RenameMode<ArmISA::ISA>::mode(src->pcState());
215 return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
237 // mode.
373 badMode32(ThreadContext *tc, OperatingMode mode) argument
375 return unknownMode32(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
379 badMode(ThreadContext *tc, OperatingMode mode) argument
381 return unknownMode(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
703 OperatingMode mode = MODE_UNDEFINED; local
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H A Dstage2_lookup.hh66 BaseTLB::Mode mode; member in class:ArmISA::Stage2LookUp
81 transState(_transState), mode(_mode), timing(_timing),
92 void mergeTe(const RequestPtr &req, BaseTLB::Mode mode);
101 BaseTLB::Mode mode);
H A Dstage2_lookup.cc60 fault = stage2Tlb->getTE(&stage2Te, req, tc, mode, this, timing,
70 fault = stage2Tlb->checkPermissions64(stage2Te, req, mode, tc);
72 fault = stage2Tlb->checkPermissions(stage2Te, req, mode);
75 mergeTe(req, mode);
82 Stage2LookUp::mergeTe(const RequestPtr &req, BaseTLB::Mode mode) argument
180 ThreadContext *tc, BaseTLB::Mode mode)
185 fault = stage2Tlb->getTE(&stage2Te, req, tc, mode, this,
191 mergeTe(req, mode);
195 transState->finish(fault, s1Req, tc, mode);
199 stage1Tlb->translateComplete(s1Req, tc, transState, mode, tranTyp
179 finish(const Fault &_fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode) argument
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/gem5/src/arch/arm/insts/
H A Dfplib.cc390 fp16_unpack(int *sgn, int *exp, uint16_t *mnt, uint16_t x, int mode, argument
403 if (mode & FPLIB_FZ16)
409 fp32_unpack(int *sgn, int *exp, uint32_t *mnt, uint32_t x, int mode, argument
421 if ((mode & FPLIB_FZ) && *mnt) {
429 fp64_unpack(int *sgn, int *exp, uint64_t *mnt, uint64_t x, int mode, argument
441 if ((mode & FPLIB_FZ) && *mnt) {
521 fp16_process_NaN(uint16_t a, int mode, int *flags) argument
527 return mode & FPLIB_DN ? fp16_defaultNaN() : a;
531 fp32_process_NaN(uint32_t a, int mode, int *flags) argument
537 return mode
541 fp64_process_NaN(uint64_t a, int mode, int *flags) argument
551 fp16_process_NaNs(uint16_t a, uint16_t b, int mode, int *flags) argument
574 fp32_process_NaNs(uint32_t a, uint32_t b, int mode, int *flags) argument
597 fp64_process_NaNs(uint64_t a, uint64_t b, int mode, int *flags) argument
620 fp16_process_NaNs3(uint16_t a, uint16_t b, uint16_t c, int mode, int *flags) argument
649 fp32_process_NaNs3(uint32_t a, uint32_t b, uint32_t c, int mode, int *flags) argument
678 fp64_process_NaNs3(uint64_t a, uint64_t b, uint64_t c, int mode, int *flags) argument
707 fp16_round_(int sgn, int exp, uint16_t mnt, int rm, int mode, int *flags) argument
785 fp16_round(int sgn, int exp, uint16_t mnt, int mode, int *flags) argument
791 fp32_round_(int sgn, int exp, uint32_t mnt, int rm, int mode, int *flags) argument
862 fp32_round(int sgn, int exp, uint32_t mnt, int mode, int *flags) argument
868 fp64_round_(int sgn, int exp, uint64_t mnt, int rm, int mode, int *flags) argument
939 fp64_round(int sgn, int exp, uint64_t mnt, int mode, int *flags) argument
945 fp16_compare_eq(uint16_t a, uint16_t b, int mode, int *flags) argument
964 fp16_compare_ge(uint16_t a, uint16_t b, int mode, int *flags) argument
989 fp16_compare_gt(uint16_t a, uint16_t b, int mode, int *flags) argument
1014 fp16_compare_un(uint16_t a, uint16_t b, int mode, int *flags) argument
1033 fp32_compare_eq(uint32_t a, uint32_t b, int mode, int *flags) argument
1052 fp32_compare_ge(uint32_t a, uint32_t b, int mode, int *flags) argument
1077 fp32_compare_gt(uint32_t a, uint32_t b, int mode, int *flags) argument
1102 fp32_compare_un(uint32_t a, uint32_t b, int mode, int *flags) argument
1121 fp64_compare_eq(uint64_t a, uint64_t b, int mode, int *flags) argument
1140 fp64_compare_ge(uint64_t a, uint64_t b, int mode, int *flags) argument
1165 fp64_compare_gt(uint64_t a, uint64_t b, int mode, int *flags) argument
1190 fp64_compare_un(uint64_t a, uint64_t b, int mode, int *flags) argument
1209 fp16_add(uint16_t a, uint16_t b, int neg, int mode, int *flags) argument
1269 fp32_add(uint32_t a, uint32_t b, int neg, int mode, int *flags) argument
1329 fp64_add(uint64_t a, uint64_t b, int neg, int mode, int *flags) argument
1389 fp16_mul(uint16_t a, uint16_t b, int mode, int *flags) argument
1426 fp32_mul(uint32_t a, uint32_t b, int mode, int *flags) argument
1463 fp64_mul(uint64_t a, uint64_t b, int mode, int *flags) argument
1500 fp16_muladd(uint16_t a, uint16_t b, uint16_t c, int scale, int mode, int *flags) argument
1585 fp32_muladd(uint32_t a, uint32_t b, uint32_t c, int scale, int mode, int *flags) argument
1670 fp64_muladd(uint64_t a, uint64_t b, uint64_t c, int scale, int mode, int *flags) argument
1762 fp16_div(uint16_t a, uint16_t b, int mode, int *flags) argument
1804 fp32_div(uint32_t a, uint32_t b, int mode, int *flags) argument
1846 fp64_div(uint64_t a, uint64_t b, int mode, int *flags) argument
1924 fp16_scale(uint16_t a, int16_t b, int mode, int *flags) argument
1958 fp32_scale(uint32_t a, int32_t b, int mode, int *flags) argument
1992 fp64_scale(uint64_t a, int64_t b, int mode, int *flags) argument
2026 fp16_sqrt(uint16_t a, int mode, int *flags) argument
2078 fp32_sqrt(uint32_t a, int mode, int *flags) argument
2133 fp64_sqrt(uint64_t a, int mode, int *flags) argument
2411 int mode = modeConv(fpscr); local
2445 int mode = modeConv(fpscr); local
2479 int mode = modeConv(fpscr); local
2615 int mode = modeConv(fpscr); local
2664 int mode = modeConv(fpscr); local
2713 int mode = modeConv(fpscr); local
2751 int mode = modeConv(fpscr); local
2790 int mode = modeConv(fpscr); local
2828 int mode = modeConv(fpscr); local
3170 int mode = modeConv(fpscr); local
3193 int mode = modeConv(fpscr); local
3216 int mode = modeConv(fpscr); local
3263 int mode = modeConv(fpscr); local
3286 int mode = modeConv(fpscr); local
3309 int mode = modeConv(fpscr); local
3386 int mode = modeConv(fpscr); local
3417 int mode = modeConv(fpscr); local
3448 int mode = modeConv(fpscr); local
3519 int mode = modeConv(fpscr); local
3554 int mode = modeConv(fpscr); local
3589 int mode = modeConv(fpscr); local
3624 int mode = modeConv(fpscr); local
3654 int mode = modeConv(fpscr); local
3684 int mode = modeConv(fpscr); local
3714 int mode = modeConv(fpscr); local
3776 int mode = modeConv(fpscr); local
3838 int mode = modeConv(fpscr); local
3900 int mode = modeConv(fpscr); local
3930 int mode = modeConv(fpscr); local
3960 int mode = modeConv(fpscr); local
3990 int mode = modeConv(fpscr); local
4017 int mode = modeConv(fpscr); local
4044 int mode = modeConv(fpscr); local
4072 int mode = modeConv(fpscr); local
4202 int mode = modeConv(fpscr); local
4462 int mode = modeConv(fpscr); local
4482 int mode = modeConv(fpscr); local
4501 int mode = modeConv(fpscr); local
4829 fp16_cvtf(uint64_t a, int fbits, int u, int mode, int *flags) argument
4849 fp32_cvtf(uint64_t a, int fbits, int u, int mode, int *flags) argument
4869 fp64_cvtf(uint64_t a, int fbits, int u, int mode, int *flags) argument
[all...]
/gem5/src/cpu/testers/traffic_gen/
H A Dtraffic_gen.cc86 DPRINTF(TrafficGen, "Timing mode, activating request generator\n");
90 "Traffic generator is only active in timing mode\n");
169 string mode; local
171 is >> id >> duration >> mode; local
173 if (mode == "TRACE") {
182 } else if (mode == "IDLE") {
185 } else if (mode == "EXIT") {
188 } else if (mode == "LINEAR" || mode == "RANDOM" ||
189 mode
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/gem5/src/dev/x86/
H A DI8259.py46 mode = Param.X86I8259CascadeMode('How this I8259 is cascaded') variable in class:I8259
/gem5/ext/pybind11/include/pybind11/
H A Deval.h29 template <eval_mode mode = eval_expr>
39 switch (mode) {
43 default: pybind11_fail("invalid evaluation mode");
52 template <eval_mode mode = eval_expr, size_t N>
57 return eval<mode>(expr, global, local);
69 template <eval_mode mode = eval_statements>
75 switch (mode) {
79 default: pybind11_fail("invalid evaluation mode");
/gem5/util/plot_dram/
H A Ddram_sweep_plot.py68 # Choose the appropriate mode, either utilisation, total power, or
70 mode = sys.argv[1][1]
136 if mode == 'u':
138 elif mode == 'p':
140 elif mode == 'e':
144 print "Unexpected mode %s" % mode
180 if mode == 'u':
182 elif mode == 'p':
184 elif mode
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/gem5/src/arch/arm/tracers/
H A Dtarmac_base.cc72 mode(MODE_USER)
75 // Operating mode gained by reading the architectural register (CPSR)
77 mode = (OperatingMode) (uint8_t)cpsr.mode;

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