Searched refs:min_w_nmos_ (Results 1 - 15 of 15) sorted by relevance

/gem5/ext/mcpat/cacti/
H A Dcrossbar.cc44 min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * g_tp.min_w_nmos_;
67 double input_cap = gate_C(TriS1 * (2 * min_w_pmos + g_tp.min_w_nmos_), 0) +
68 gate_C(TriS1 * (min_w_pmos + 2 * g_tp.min_w_nmos_), 0);
69 // input_cap += drain_C_(TriS1*g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) +
71 // gate_C(TriS2*g_tp.min_w_nmos_, 0)+
75 tri_int_cap = drain_C_(TriS1 * g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) +
77 gate_C(TriS2 * g_tp.min_w_nmos_, 0) +
81 double output_cap = drain_C_(TriS2 * g_tp.min_w_nmos_, NCH, 1, 1,
84 double ctr_cap = gate_C(TriS2 * (min_w_pmos + g_tp.min_w_nmos_), 0);
98 double g_area = compute_gate_area(INV, 1, TriS2 * g_tp.min_w_nmos_,
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H A Dwire.cc49 min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * g_tp.min_w_nmos_;
89 min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * g_tp.min_w_nmos_;
157 g_tp.min_w_nmos_ * repeater_size,
168 g_tp.min_w_nmos_ * repeater_size,
179 g_tp.min_w_nmos_ * repeater_size,
190 g_tp.min_w_nmos_ * repeater_size,
201 g_tp.min_w_nmos_ * repeater_size,
231 timeconst = (drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) +
233 gate_C(min_w_pmos + g_tp.min_w_nmos_, 0)) *
238 timeconst = (drain_C_(g_tp.min_w_nmos_, NC
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H A Darbiter.cc42 min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * g_tp.min_w_nmos_;
96 double nor1_leak = cmos_Isub_leakage(g_tp.min_w_nmos_ * NTn1 * 2,
98 double nor2_leak = cmos_Isub_leakage(g_tp.min_w_nmos_ * NTn2 * R,
100 double not_leak = cmos_Isub_leakage(g_tp.min_w_nmos_ * NTi,
102 double nor1_leak_gate = cmos_Ig_leakage(g_tp.min_w_nmos_ * NTn1 * 2,
104 double nor2_leak_gate = cmos_Ig_leakage(g_tp.min_w_nmos_ * NTn2 * R,
106 double not_leak_gate = cmos_Ig_leakage(g_tp.min_w_nmos_ * NTi,
H A Dcomponent.cc198 w_n[i] = MAX(w_n[i], g_tp.min_w_nmos_);
214 w_n[i] = MAX(w_n[i+1] / f, g_tp.min_w_nmos_);
H A Ddecoder.cc113 w_dec_n[0] = 2 * g_tp.min_w_nmos_;
114 w_dec_p[0] = p_to_n_sz_ratio * g_tp.min_w_nmos_;
117 w_dec_n[0] = 3 * g_tp.min_w_nmos_;
118 w_dec_p[0] = p_to_n_sz_ratio * g_tp.min_w_nmos_;
410 w_L2_n[0] = 2 * g_tp.min_w_nmos_;
413 w_L2_n[0] = 3 * g_tp.min_w_nmos_;
416 w_L2_p[0] = p_to_n_sz_ratio * g_tp.min_w_nmos_;
439 w_L1_nand2_n[0] = 2 * g_tp.min_w_nmos_;
440 w_L1_nand2_p[0] = p_to_n_sz_ratio * g_tp.min_w_nmos_;
463 w_L1_nand3_n[0] = 3 * g_tp.min_w_nmos_;
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H A Drouter.cc52 min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * g_tp.min_w_nmos_;
218 cmos_Isub_leakage(NTtr * g_tp.min_w_nmos_, PTtr * min_w_pmos, 1, tg);
220 cmos_Ig_leakage(NTtr * g_tp.min_w_nmos_, PTtr * min_w_pmos, 1, tg);
H A Dmat.cc632 pmos_to_nmos_sz_ratio(is_dram) * g_tp.min_w_nmos_, cell.w * dp.Ndsam_lev_2 / (RWP + ERP));
633 height += 2 * compute_tr_width_after_folding(g_tp.min_w_nmos_, cell.w * dp.Ndsam_lev_2 / (RWP + ERP));
723 W_hit_miss_p = g_tp.min_w_nmos_*p_to_n_sizing_r;
755 W_hit_miss_p = g_tp.min_w_nmos_*p_to_n_sizing_r;
1277 gate_C(g_tp.min_w_nmos_ + p_to_n_sz_r * g_tp.min_w_nmos_, 0.0, is_dram);
1288 rd = tr_R_on(g_tp.min_w_nmos_, NCH, 1, is_dram);
1289 C_ld = drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def, is_dram) +
1290 drain_C_(p_to_n_sz_r * g_tp.min_w_nmos_, PCH, 1, 1, g_tp.cell_h_def, is_dram) +
1291 gate_C(g_tp.min_w_nmos_
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H A Dparameter.h168 double min_w_nmos_; member in class:TechnologyParameter
H A Dtechnology.cc1751 g_tp.min_w_nmos_ = 3 * g_ip->F_sz_um / 2;
1762 g_tp.w_nmos_b_mux = 6 * g_tp.min_w_nmos_;
1763 g_tp.w_nmos_sa_mux= 6 * g_tp.min_w_nmos_;
1798 g_tp.w_pmos_bl_precharge = 6 * pmos_to_nmos_sizing_r * g_tp.min_w_nmos_;
1799 g_tp.w_pmos_bl_eq = pmos_to_nmos_sizing_r * g_tp.min_w_nmos_;
2650 double rd = tr_R_on(g_tp.min_w_nmos_, NCH, 1);
2652 double c_load = gate_C(g_tp.min_w_nmos_ * (1 + p_to_n_sizing_r), 0.0);
2656 c_load = KLOAD * (drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) +
2657 drain_C_(g_tp.min_w_nmos_ * p_to_n_sizing_r, PCH, 1, 1, g_tp.cell_h_def) +
2658 gate_C(g_tp.min_w_nmos_ *
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H A Dparameter.cc106 cout << indent_str << "min_w_nmos_ = " << setw(12) << min_w_nmos_ << " um" << endl;
H A Dhtree2.cc68 min_w_nmos = g_tp.min_w_nmos_;
/gem5/ext/mcpat/
H A Dlogic.cc339 WNANDn = (process_ind) ? 25 * l_ip.F_sz_um : g_tp.min_w_nmos_ ;
341 WNANDp = (process_ind) ? 37.5 * l_ip.F_sz_um : g_tp.min_w_nmos_ *
528 leakage = area_t *(g_tp.scaling_factor.core_tx_density)*cmos_Isub_leakage(5*g_tp.min_w_nmos_, 5*g_tp.min_w_nmos_*pmos_to_nmos_sizing_r, 1, inv)*g_tp.peri_global.Vdd/2;//unit W
529 gate_leakage = area_t *(g_tp.scaling_factor.core_tx_density)*cmos_Ig_leakage(5*g_tp.min_w_nmos_, 5*g_tp.min_w_nmos_*pmos_to_nmos_sizing_r, 1, inv)*g_tp.peri_global.Vdd/2;//unit W
540 leakage = area_t *(g_tp.scaling_factor.core_tx_density)*cmos_Isub_leakage(20*g_tp.min_w_nmos_, 20*g_tp.min_w_nmos_*pmos_to_nmos_sizing_r, 1, inv)*g_tp.peri_global.Vdd/2;//unit W
541 gate_leakage = area_t*(g_tp.scaling_factor.core_tx_density)*cmos_Ig_leakage(20*g_tp.min_w_nmos_, 20*g_tp.min_w_nmos_*pmos_to_nmos_sizing_
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H A Diocontrollers.cc150 NMOS_sizing = 5 * g_tp.min_w_nmos_;
151 PMOS_sizing = 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r;
169 NMOS_sizing = g_tp.min_w_nmos_;
170 PMOS_sizing = g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r;
308 NMOS_sizing = 5 * g_tp.min_w_nmos_;
309 PMOS_sizing = 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r;
326 NMOS_sizing = g_tp.min_w_nmos_;
327 PMOS_sizing = g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r;
455 NMOS_sizing = 5 * g_tp.min_w_nmos_;
456 PMOS_sizing = 5 * g_tp.min_w_nmos_ * pmos_to_nmos_sizing_
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H A Dmemoryctrl.cc116 double NMOS_sizing = g_tp.min_w_nmos_;
117 double PMOS_sizing = g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r;
251 double NMOS_sizing = g_tp.min_w_nmos_;
252 double PMOS_sizing = g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r;
H A Dinterconnect.cc67 min_w_nmos = g_tp.min_w_nmos_;

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