Searched refs:mem_master_port (Results 1 - 4 of 4) sorted by relevance

/gem5/src/mem/ruby/system/
H A DSequencer.py43 mem_master_port = MasterPort("Ruby mem master port") variable in class:RubyPort
/gem5/configs/ruby/
H A DRuby.py214 cpu_seq.mem_master_port = piobus.slave
/gem5/tests/configs/
H A Dgpu-ruby.py297 system.ruby._cpu_ports[0].mem_master_port = system.piobus.slave
/gem5/configs/example/
H A Dapu_se.py462 ruby_port.mem_master_port = system.piobus.slave

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