| /gem5/src/mem/probes/ |
| H A D | StackDistProbe.py | 51 line_size = Param.Unsigned(Parent.cache_line_size, variable in class:StackDistProbe
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| H A D | stack_dist.cc | 47 lineSize(p->line_size),
52 fatal_if(p->system->cacheLineSize() > p->line_size,
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| /gem5/configs/common/ |
| H A D | FileSystemConfig.py | 175 def register_cache(level, idu_type, size, line_size, assoc, cpus):
190 file_append((indexdir, 'coherency_line_size'), line_size)
193 num_sets = toMemorySize(size) / int(assoc) * int(line_size)
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| /gem5/configs/ruby/ |
| H A D | MESI_Three_Level.py | 276 line_size = options.cacheline_size,
282 line_size = options.cacheline_size,
289 line_size = options.cacheline_size,
297 line_size = options.cacheline_size,
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| H A D | MOESI_AMD_Base.py | 347 line_size = options.cacheline_size,
354 line_size = options.cacheline_size,
361 line_size = options.cacheline_size,
368 line_size = options.cacheline_size,
376 line_size = options.cacheline_size,
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| H A D | MOESI_hammer.py | 270 line_size = options.cacheline_size,
276 line_size = options.cacheline_size,
283 line_size = options.cacheline_size,
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| H A D | GPU_VIPER.py | 520 line_size = options.cacheline_size,
527 line_size = options.cacheline_size,
534 line_size = options.cacheline_size,
541 line_size = options.cacheline_size,
549 line_size = options.cacheline_size,
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| /gem5/ext/mcpat/cacti/ |
| H A D | cacti_interface.h | 350 int line_size,
405 int line_size,
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| H A D | io.cc | 673 int line_size,
742 g_ip->line_sz = line_size;
863 int line_size,
932 g_ip->line_sz = line_size;
671 cacti_interface( int cache_size, int line_size, int associativity, int rw_ports, int excl_read_ports, int excl_write_ports, int single_ended_read_ports, int banks, double tech_node, int page_sz, int burst_length, int pre_width, int output_width, int specific_tag, int tag_width, int access_mode, int cache, int main_mem, int obj_func_delay, int obj_func_dynamic_power, int obj_func_leakage_power, int obj_func_area, int obj_func_cycle_time, int dev_func_delay, int dev_func_dynamic_power, int dev_func_leakage_power, int dev_func_area, int dev_func_cycle_time, int ed_ed2_none, int temp, int wt, int data_arr_ram_cell_tech_flavor_in, int data_arr_peri_global_tech_flavor_in, int tag_arr_ram_cell_tech_flavor_in, int tag_arr_peri_global_tech_flavor_in, int interconnect_projection_type_in, int wire_inside_mat_type_in, int wire_outside_mat_type_in, int is_nuca, int core_count, int cache_level, int nuca_bank_count, int nuca_obj_func_delay, int nuca_obj_func_dynamic_power, int nuca_obj_func_leakage_power, int nuca_obj_func_area, int nuca_obj_func_cycle_time, int nuca_dev_func_delay, int nuca_dev_func_dynamic_power, int nuca_dev_func_leakage_power, int nuca_dev_func_area, int nuca_dev_func_cycle_time, int REPEATERS_IN_HTREE_SEGMENTS_in, int p_input) argument
861 cacti_interface( int cache_size, int line_size, int associativity, int rw_ports, int excl_read_ports, int excl_write_ports, int single_ended_read_ports, int search_ports, int banks, double tech_node, int output_width, int specific_tag, int tag_width, int access_mode, int cache, int main_mem, int obj_func_delay, int obj_func_dynamic_power, int obj_func_leakage_power, int obj_func_cycle_time, int obj_func_area, int dev_func_delay, int dev_func_dynamic_power, int dev_func_leakage_power, int dev_func_area, int dev_func_cycle_time, int ed_ed2_none, int temp, int wt, int data_arr_ram_cell_tech_flavor_in, int data_arr_peri_global_tech_flavor_in, int tag_arr_ram_cell_tech_flavor_in, int tag_arr_peri_global_tech_flavor_in, int interconnect_projection_type_in, int wire_inside_mat_type_in, int wire_outside_mat_type_in, int REPEATERS_IN_HTREE_SEGMENTS_in, int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in, int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in, int PAGE_SIZE_BITS_in, int BURST_LENGTH_in, int INTERNAL_PREFETCH_WIDTH_in, int force_wiretype, int wiretype, int force_config, int ndwl, int ndbl, int nspd, int ndcm, int ndsam1, int ndsam2, int ecc) argument
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| /gem5/src/dev/arm/ |
| H A D | hdlcd.cc | 606 size_t line_size, ssize_t line_pitch, unsigned num_lines)
611 lineSize(line_size), linePitch(line_pitch), numLines(num_lines),
604 DmaEngine(HDLcd &_parent, size_t size, unsigned request_size, unsigned max_pending, size_t line_size, ssize_t line_pitch, unsigned num_lines) argument
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| H A D | hdlcd.hh | 372 size_t line_size, ssize_t line_pitch, unsigned num_lines);
|