Searched refs:lId (Results 1 - 3 of 3) sorted by relevance
| /gem5/src/cpu/o3/ |
| H A D | thread_context.hh | 463 readVecLaneFlat(RegIndex idx, int lId) const
465 return cpu->template readArchVecLane<VecElem>(idx, lId,
471 setVecLaneFlat(int idx, int lId, const LD& val) argument
473 cpu->template setArchVecLane(idx, lId, thread->threadId(), val);
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| H A D | cpu.hh | 435 readArchVecLane(int reg_idx, int lId, ThreadID tid) const argument
446 setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val) argument
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| /gem5/src/cpu/ |
| H A D | simple_thread.hh | 640 readVecLaneFlat(RegIndex reg, int lId) const
642 return vecRegs[reg].laneView<T>(lId);
647 setVecLaneFlat(RegIndex reg, int lId, const LD &val) argument
649 vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val;
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