Searched refs:isWrite (Results 1 - 25 of 49) sorted by relevance

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/gem5/util/tlm/src/
H A Dsc_slave_port.cc76 } else if (packet->isWrite()) {
95 panic_if(!(packet->isRead() || packet->isWrite()),
118 } else if (packet->isWrite()) {
183 panic_if(!(packet->isRead() || packet->isWrite()),
/gem5/src/cpu/testers/traffic_gen/
H A Dbase_gen.cc76 if (cmd.isWrite()) {
/gem5/src/mem/
H A Dmem_delay.cc184 } else if (pkt->isWrite()) {
196 } else if (pkt->isWrite()) {
H A Dpacket.hh200 bool isWrite() const { return testCmdAttrib(IsWrite); } function in class:MemCmd
531 bool isWrite() const { return cmd.isWrite(); } function
671 assert(cmd.isWrite() &&
777 assert(isWrite());
966 if (isWrite()) {
H A Dabstract_mem.cc390 assert(!pkt->isWrite());
406 assert(!pkt->isWrite());
411 } else if (pkt->isWrite()) {
445 } else if (pkt->isWrite()) {
H A Dcomm_monitor.cc277 } else if (pkt_info.cmd.isWrite()) {
332 } else if (pkt_info.cmd.isWrite()) {
406 pkt->isWrite() ? "write" : "non read/write");
455 pkt->isWrite() ? "write" : "non read/write");
H A Ddramsim2.cc206 } else if (pkt->isWrite()) {
231 wrapper.enqueue(pkt->isWrite(), pkt->getAddr());
H A Dmem_checker_monitor.cc146 bool is_write = pkt->isWrite();
235 bool is_write = pkt->isWrite();
H A Dcoherent_xbar.cc281 if (pkt->isWrite() && is_destination) {
381 PacketPtr deferred_rsp = pkt->isWrite() ? nullptr : pkt;
386 if (pkt->isWrite()) {
403 if (!pkt->isWrite()) {
799 if (pkt->isWrite() && is_destination) {
1082 (pointOfCoherency && !(pkt->isRead() || pkt->isWrite()) &&
1100 return pkt->isRead() || pkt->isWrite() || !pointOfCoherency;
H A Dsimple_mem.cc117 panic_if(!(pkt->isRead() || pkt->isWrite()),
/gem5/src/mem/probes/
H A Dstack_dist.cc103 if (!pkt_info.cmd.isRead() && !pkt_info.cmd.isWrite())
/gem5/src/cpu/testers/memtest/
H A Dmemtest.cc146 pkt->isWrite() ? "write" : "read",
155 pkt->isWrite() ? "Write" : "Read", req->getPaddr());
179 assert(pkt->isWrite());
/gem5/src/mem/cache/
H A Dnoncoherent_cache.cc78 assert(pkt->isRead() || pkt->isWrite());
143 panic_if(!(pkt->isRead() || pkt->isWrite()),
228 panic_if(!(pkt->isRead() || pkt->isWrite()),
H A Dwrite_queue_entry.cc108 panic_if(!((target->isWrite() && _isUncacheable) ||
/gem5/src/arch/arm/
H A Dlocked_mem.hh68 assert(pkt->isInvalidate() || pkt->isWrite());
H A Dtable_walker.cc136 isWrite(false), isFetch(false), isSecure(false),
304 currState->isWrite = (currState->mode == TLB::Write);
483 is_atomic ? false : currState->isWrite,
503 is_atomic ? false : currState->isWrite,
617 is_atomic ? false : currState->isWrite,
641 is_atomic ? false : currState->isWrite,
663 is_atomic ? false : currState->isWrite,
871 is_atomic ? false : currState->isWrite,
957 is_atomic ? false : currState->isWrite,
1491 is_atomic ? false : currState->isWrite,
[all...]
/gem5/src/mem/cache/prefetch/
H A Dbase.hh175 bool isWrite() const function in class:BasePrefetcher::PrefetchInfo
H A Dbase.cc62 secure(pkt->isSecure()), size(pkt->req->getSize()), write(pkt->isWrite()),
209 if (pkt->isWrite() && cache != nullptr && cache->coalesce()) return;
/gem5/src/dev/arm/
H A Dsmmu_v3_slaveifc.cc152 (pkt->isWrite() && wrBufSlotsRemaining < nbeats))
158 if (pkt->isWrite())
H A Dsmmu_v3_transl.hh54 bool isWrite; member in struct:SMMUTranslRequest
H A Dsmmu_v3_transl.cc57 req.isWrite = pkt->isWrite();
73 req.isWrite = false;
152 unsigned numSlaveBeats = request.isWrite ?
765 if (valid && leaf && request.isWrite &&
849 if (valid && leaf && request.isWrite &&
1135 request.isWrite ?
1148 request.isWrite ?
1187 request.isWrite ?
1228 unsigned numMasterBeats = request.isWrite
[all...]
/gem5/src/mem/ruby/system/
H A DRubyPort.cc393 } else if (pkt->isWrite()) {
403 pkt->isWrite() ? "write" : "read", pkt->getAddr());
509 if (pkt->isWrite()) {
/gem5/ext/sst/
H A DExtSlave.cc162 if (pkt->isLLSC() && pkt->isWrite()) {
/gem5/src/systemc/tlm_bridge/
H A Dgem5_to_tlm.cc111 } else if (packet->isWrite()) {
289 panic_if(!(packet->isRead() || packet->isWrite()),
/gem5/src/learning_gem5/part2/
H A Dsimple_cache.cc315 if (pkt->isWrite() || pkt->isRead()) {
345 if (pkt->isWrite()) {

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