Searched refs:isVectorRegister (Results 1 - 8 of 8) sorted by relevance

/gem5/src/arch/hsail/insts/
H A Ddecl.hh140 bool isVectorRegister(int operandIndex) { function in class:HsailISA::CommonInstBase
143 return src[operandIndex].isVectorRegister();
145 return dest.isVectorRegister();
194 if (src[i].isVectorRegister()) {
200 int numDstRegOperands() { return dest.isVectorRegister(); }
260 bool isVectorRegister(int operandIndex) { function in class:HsailISA::ThreeNonUniformSourceInstBase
263 return src0.isVectorRegister();
265 return src1.isVectorRegister();
267 return src2.isVectorRegister();
269 return dest.isVectorRegister();
435 bool isVectorRegister(int operandIndex) { function in class:HsailISA::TwoNonUniformSourceInstBase
827 bool isVectorRegister(int operandIndex) { function in class:HsailISA::SpecialInstNoSrcBase
902 bool isVectorRegister(int operandIndex) { function in class:HsailISA::SpecialInst1SrcBase
1242 bool isVectorRegister(int operandIndex) { return false; } function in class:HsailISA::Call
[all...]
H A Dbranch.hh71 bool isVectorRegister(int operandIndex) override {
73 return target.isVectorRegister();
158 int numSrcRegOperands() { return target.isVectorRegister(); }
190 bool isVectorRegister(int operandIndex) override {
193 return target.isVectorRegister();
327 int numSrcRegOperands() { return target.isVectorRegister(); }
356 bool isVectorRegister(int operandIndex) override {
358 return target.isVectorRegister();
433 int numSrcRegOperands() { return target.isVectorRegister(); }
H A Dmem.hh111 { return(this->addr.isVectorRegister()); }
113 { return dest.isVectorRegister(); }
114 bool isVectorRegister(int operandIndex) override
117 return((operandIndex == 0) ? dest.isVectorRegister() :
118 this->addr.isVectorRegister());
136 return(this->addr.isVectorRegister());
158 if (this->addr.isVectorRegister())
336 { return(this->addr.isVectorRegister()); }
337 int numDstRegOperands() override { return dest.isVectorRegister(); }
340 if (this->addr.isVectorRegister())
1385 bool isVectorRegister(int operandIndex) function in class:HsailISA::AtomicInstBase
[all...]
/gem5/src/gpu-compute/
H A Dvector_register_file.cc124 if (ii->isVectorRegister(i)) {
163 if (ii->isVectorRegister(i) && ii->isDstOperand(i)) {
219 if (ii->isVectorRegister(i) && ii->isDstOperand(i)) {
H A Dgpu_dyn_inst.cc94 GPUDynInst::isVectorRegister(int operandIdx) function in class:GPUDynInst
96 return _staticInst->isVectorRegister(operandIdx);
H A Dgpu_static_inst.hh82 virtual bool isVectorRegister(int operandIndex) = 0;
288 bool isVectorRegister(int operandIndex) override { return false; }
H A Dgpu_dyn_inst.hh207 bool isVectorRegister(int operandIdx);
/gem5/src/arch/hsail/
H A Doperand.hh69 bool isVectorRegister() { return registerType == Enums::RT_VECTOR; } function in class:BaseOperand
491 isVectorRegister() function in class:RegOrImmOperand
609 bool isVectorRegister() { return reg.registerType == Enums::RT_VECTOR; } function in class:RegAddrOperand

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