Searched refs:isCondRegister (Results 1 - 8 of 8) sorted by relevance

/gem5/src/gpu-compute/
H A Dcondition_register_state.cc70 if (ii->isCondRegister(i) && ii->isDstOperand(i)) {
H A Dgpu_dyn_inst.cc106 GPUDynInst::isCondRegister(int operandIdx) function in class:GPUDynInst
108 return _staticInst->isCondRegister(operandIdx);
H A Dgpu_static_inst.hh80 virtual bool isCondRegister(int operandIndex) = 0;
286 bool isCondRegister(int operandIndex) override { return false; }
H A Dgpu_dyn_inst.hh209 bool isCondRegister(int operandIdx);
/gem5/src/arch/hsail/insts/
H A Ddecl.hh147 bool isCondRegister(int operandIndex) { function in class:HsailISA::CommonInstBase
150 return src[operandIndex].isCondRegister();
152 return dest.isCondRegister();
271 bool isCondRegister(int operandIndex) { function in class:HsailISA::ThreeNonUniformSourceInstBase
274 return src0.isCondRegister();
276 return src1.isCondRegister();
278 return src2.isCondRegister();
280 return dest.isCondRegister();
444 bool isCondRegister(int operandIndex) { function in class:HsailISA::TwoNonUniformSourceInstBase
447 return src0.isCondRegister();
831 bool isCondRegister(int operandIndex) { function in class:HsailISA::SpecialInstNoSrcBase
906 bool isCondRegister(int operandIndex) { function in class:HsailISA::SpecialInst1SrcBase
1243 bool isCondRegister(int operandIndex) { return false; } function in class:HsailISA::Call
[all...]
H A Dbranch.hh75 bool isCondRegister(int operandIndex) override {
77 return target.isCondRegister();
197 bool isCondRegister(int operandIndex) override {
200 return target.isCondRegister();
360 bool isCondRegister(int operandIndex) override {
362 return target.isCondRegister();
H A Dmem.hh120 bool isCondRegister(int operandIndex) override
123 return((operandIndex == 0) ? dest.isCondRegister() :
124 this->addr.isCondRegister());
351 bool isCondRegister(int operandIndex) override
354 return((operandIndex == 0) ? dest.isCondRegister() :
355 this->addr.isCondRegister());
618 bool isCondRegister(int operandIndex) override
623 return(this->addr.isCondRegister());
625 return dest_vect[operandIndex].isCondRegister();
629 AddrOperandType>::dest.isCondRegister();
1395 bool isCondRegister(int operandIndex) function in class:HsailISA::AtomicInstBase
[all...]
/gem5/src/arch/hsail/
H A Doperand.hh71 bool isCondRegister() { return registerType == Enums::RT_CONDITION; } function in class:BaseOperand
500 isCondRegister() function in class:RegOrImmOperand
610 bool isCondRegister() { return reg.registerType == Enums::RT_CONDITION; } function in class:RegAddrOperand

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