Searched refs:interrupt (Results 1 - 25 of 32) sorted by relevance

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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/
H A Dwfi.S7 # Test wait-for-interrupt instruction.
/gem5/src/dev/mips/
H A Dmalta_cchip.cc106 MaltaCChip::postIntr(uint32_t interrupt) argument
114 malta->intrctrl->post(i, interrupt, 0);
115 DPRINTF(Malta, "posting interrupt to cpu %d, interrupt %d\n",
116 i, interrupt);
121 MaltaCChip::clearIntr(uint32_t interrupt) argument
129 malta->intrctrl->clear(i, interrupt, 0);
130 DPRINTF(Malta, "clearing interrupt to cpu %d, interrupt %d\n",
131 i, interrupt);
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H A Dmalta_cchip.hh44 * Malta CChip CSR Emulation. This device includes all the interrupt
58 * The dims are device interrupt mask registers.
64 * The dirs are device interrupt registers.
70 * This register contains bits for each PCI interrupt
75 /** Indicator of which CPUs have an IPI interrupt */
78 /** Indicator of which CPUs have an RTC interrupt */
102 * post an RTC interrupt to the CPU
107 * post an interrupt to the CPU.
108 * @param interrupt the interrupt numbe
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H A Dmalta_io.hh65 //Actually interrupt the processor here
82 /** Raw PIC interrupt register before masking */
105 * @return interrupt rate of the RTC
128 void postIntr(uint8_t interrupt);
131 void clearIntr(uint8_t interrupt);
H A Dmalta_io.cc99 MaltaIO::postIntr(uint8_t interrupt) argument
101 malta->cchip->postIntr(interrupt);
102 DPRINTF(Malta, "posting pic interrupt to cchip\n");
106 MaltaIO::clearIntr(uint8_t interrupt) argument
108 malta->cchip->clearIntr(interrupt);
109 DPRINTF(Malta, "clear pic interrupt to cchip\n");
/gem5/src/dev/arm/
H A DVirtIOMMIO.py53 interrupt = Param.ArmInterruptPin("Interrupt to use for this device") variable in class:MmioVirtIO
60 int(self.interrupt.num),
H A Dvio_mmio.cc52 interrupt(params->interrupt->get())
54 fatal_if(!interrupt, "No MMIO VirtIO interrupt specified\n");
263 DPRINTF(VIOIface, "kick(): Sending interrupt...\n");
274 interrupt->raise();
276 interrupt->clear();
H A Dvio_mmio.hh112 ArmInterruptPin *const interrupt; member in class:MmioVirtIO
H A Dgeneric_timer.hh141 * trigger condition and raise interrupt if necessary.
155 ArmInterruptPin *interrupt);
203 ArmInterruptPin *interrupt)
204 : ArchTimer(name, parent, sysctr, interrupt), system(system) {}
199 ArchTimerKvm(const std::string &name, ArmSystem &system, SimObject &parent, SystemCounter &sysctr, ArmInterruptPin *interrupt) argument
/gem5/src/dev/alpha/
H A Dtsunami_cchip.hh43 * Tsunami CChip CSR Emulation. This device includes all the interrupt
57 * The dims are device interrupt mask registers.
63 * The dirs are device interrupt registers.
69 * This register contains bits for each PCI interrupt
74 /** Indicator of which CPUs have an IPI interrupt */
77 /** Indicator of which CPUs have an RTC interrupt */
100 * post an RTC interrupt to the CPU
105 * post an interrupt to the CPU.
106 * @param interrupt the interrupt numbe
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H A Dtsunami_cchip.cc232 " interrupt to cpu %d\n", number);
241 " dir interrupt to cpu %d\n", number);
271 //If it is the 4-7th bit, clear the RTC interrupt
324 DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n");
333 " dir interrupt to cpu %d\n",
416 DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
462 DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d\n", i);
469 TsunamiCChip::postDRIR(uint32_t interrupt) argument
471 uint64_t bitvector = ULL(1) << interrupt;
479 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
487 clearDRIR(uint32_t interrupt) argument
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/gem5/ext/nomali/tests/
H A Dnomali_test_ints.c40 .func.interrupt = on_int,
46 .func.interrupt = NULL,
50 * Raise an interrupt without callbacks
67 * Register callbacks and raise interrupt again.
71 test_diag("Got spurious interrupt\n");
86 * Register mask interrupts and raise interrupt again.
/gem5/src/arch/arm/
H A Dpmu.cc70 interrupt(nullptr)
79 warn_if(!p->interrupt, "ARM PMU: No interrupt specified, interrupt " \
102 if (pmu_params->interrupt)
103 interrupt = pmu_params->interrupt->get(tc);
670 if (interrupt) {
671 DPRINTF(PMUVerbose, "Delivering PMU interrupt.\n");
672 interrupt
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H A Dinterrupts.hh98 panic("No support for other interrupt indexes\n");
113 panic("No support for other interrupt indexes\n");
172 * is an interrupt pending, even if it's masked, wfi doesn't sleep.
206 * Check the state of a particular interrupt, ignoring CPSR masks.
212 * @param interrupt Interrupt type to check the state of.
213 * @return true if the interrupt is asserted, false otherwise.
216 checkRaw(InterruptTypes interrupt) const
218 if (interrupt >= NumInterruptTypes)
221 return interrupts[interrupt];
233 // virtual interrupt, an
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H A DArmPMU.py177 interrupt = Param.ArmInterruptPin("PMU interrupt") variable in class:ArmPMU
H A Dpmu.hh198 protected: /* High-level register and interrupt handling */
217 * Deliver a PMU interrupt to the GIC
222 * Clear a PMU interrupt.
282 * the overflow interrupt can be raised/cleared as a side effect
621 /** Performance monitor interrupt number */
622 ArmInterruptPin *interrupt; member in class:ArmISA::PMU
/gem5/ext/nomali/include/libnomali/
H A Dnomali.h82 /** Model is signalling an interrupt */
122 * @param set Non-zero if raising an interrupt, zero if clearing.
124 void (*interrupt)(nomali_handle_t h, void *usr, member in union:__anon6::__anon7
310 * Get the state of an interrupt line
312 * This function queries the state of one of the GPU's interrupt
313 * lines. The state of the interrupt line is returned in 'state',
314 * which is 1 if the interrupt is being asserted and 0 otherwise. The
319 * @param[out] state Pointer to output, 1 if the interrupt is
326 * @error NOMALI_E_INVALID if an invalid interrupt was specified or if
/gem5/src/cpu/o3/
H A Dcommit_impl.hh129 interrupt = NoFault;
438 interrupt == NoFault;
738 // Verify that we still have an interrupt to handle
740 DPRINTF(Commit, "Pending interrupt is cleared by master before "
743 interrupt = NoFault;
749 // the interrupt.
752 // an interrupt needed to be handled.
755 // Clear the interrupt now that it's going to be handled
765 // CPU will handle interrupt. Note that we ignore the local copy of
766 // interrupt
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H A Dcommit.hh284 /** Handles processing an interrupt. */
287 /** Get fetch redirecting so we can handle an interrupt */
437 /** The interrupt fault. */
438 Fault interrupt; member in class:DefaultCommit
467 /** True if last committed microop can be followed by an interrupt */
470 /** Have we had an interrupt pending and then seen it de-asserted because
/gem5/ext/nomali/lib/
H A Dnomali_api.cc210 if (c.func.interrupt)
211 c.func.interrupt(static_cast<nomali_handle_t>(this), c.usr, intno, set);
/gem5/src/python/m5/util/
H A Dfdthelper.py146 def interruptCells(self, interrupt):
149 return self.int_to_cells(interrupt, self.interrupt_cells)
165 """Return an #interrupt-cells property for cpu nodes with the value
167 return FdtPropertyWords("#interrupt-cells", self.interrupt_cells)
/gem5/src/cpu/simple/
H A Dbase.cc456 Fault interrupt = interrupts[curThread]->getInterrupt(tc); local
458 if (interrupt != NoFault) {
461 interrupt->invoke(tc);
/gem5/src/dev/pci/
H A Dcopy_engine_defs.hh122 ADD_FIELD8(interrupt,2,1);
/gem5/src/cpu/kvm/
H A Dbase.hh74 * into the VM. In order to deliver an interrupt, the implementation
318 * Send a non-maskable interrupt to the guest
325 * Send a normal interrupt to the guest
328 * is set prior to calling this function. If not, an interrupt
332 * @param interrupt Structure describing the interrupt to send
334 void kvmInterrupt(const struct kvm_interrupt &interrupt);
461 * The guest exited because an interrupt window was requested
463 * The guest exited because an interrupt window was requested
H A Dx86_cpu.cc358 events.interrupt.injected, events.interrupt.nr,
359 events.interrupt.soft);
771 // Clear the interrupt bitmap
1138 // Migrate to the interrupt controller's thread to get the
1139 // interrupt. Even though the individual methods are safe to
1153 DPRINTF(KvmInt, "INIT interrupt\n");
1160 // interrupt before restarting the thread. The simulated CPUs
1164 DPRINTF(KvmInt, "STARTUP interrupt\n");
1173 DPRINTF(KvmInt, "Delivering interrupt
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