Searched refs:hit (Results 1 - 11 of 11) sorted by relevance
/gem5/ext/mcpat/ |
H A D | cachearray.h | 102 sbt_stats_p->readAc.hit * 109 sbt_stats_p->writeAc.hit *
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H A D | basic_components.h | 117 double hit; member in class:statsComponents 120 statsComponents() : access(0), hit(0), miss(0) {} 126 hit = rhs.hit; 132 hit = 0;
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H A D | basic_components.cc | 329 z.hit = x.hit + y.hit; 339 z.hit = x.hit * y[1];
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H A D | cachearray.cc | 272 tdp_stats.readAc.hit + 277 tdp_stats.writeAc.hit +
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H A D | cacheunit.cc | 138 arrayPtr->tdp_stats.readAc.hit = arrayPtr->tdp_stats.readAc.access - 144 arrayPtr->tdp_stats.writeAc.hit = arrayPtr->tdp_stats.writeAc.access - 148 arrayPtr->tdp_stats.searchAc.hit = 0; 186 arrayPtr->sbt_tdp_stats.readAc.hit = 194 arrayPtr->sbt_tdp_stats.writeAc.hit = 210 arrayPtr->sbt_rtp_stats.writeAc.hit =
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H A D | core.cc | 135 * 3) When ID stage finds out current instruction is not a branch while BTB had a hit.(mark as invalid) 3118 itlb->tdp_stats.readAc.hit = itlb->tdp_stats.readAc.access - 3141 dtlb->tdp_stats.readAc.hit = dtlb->tdp_stats.readAc.access -
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ui/ |
H A D | fence_i.S | 20 # test I$ hit 29 # test prefetcher hit
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/gem5/src/mem/cache/prefetch/ |
H A D | pif.cc | 78 bool hit = (pc > trigger) ? local 80 if (hit && update) { 87 return hit; 95 bool hit = false; local 97 hit = blk_distance <= succ.size() && succ[blk_distance - 1]; 99 hit = blk_distance <= prec.size() && succ[blk_distance - 1]; 101 hit = true; 103 return hit;
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/gem5/src/mem/ruby/structures/ |
H A D | Prefetcher.cc | 171 bool hit = accessUnitFilter(m_unit_filter, m_unit_filter_hit, local 177 if (hit) { 178 DPRINTF(RubyPrefetcher, " *** hit in unit stride buffer\n"); 182 hit = accessUnitFilter(m_negative_filter, m_negative_filter_hit, 188 if (hit) { 189 DPRINTF(RubyPrefetcher, " *** hit in unit negative unit buffer\n"); 195 hit = accessNonunitFilter(address, &stride, alloc); 200 if (hit) { 201 DPRINTF(RubyPrefetcher, " *** hit in non-unit stride buffer\n"); 210 DPRINTF(RubyPrefetcher, "Observed partial hit fo [all...] |
/gem5/src/learning_gem5/part2/ |
H A D | simple_cache.cc | 233 // the cache access now. It better be a hit. 234 bool hit M5_VAR_USED = accessFunctional(originalPacket); 235 panic_if(!hit, "Should always hit after inserting"); 284 bool hit = accessFunctional(pkt); local 286 DPRINTF(SimpleCache, "%s for packet: %s\n", hit ? "Hit" : "Miss", 289 if (hit) {
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/gem5/src/dev/arm/ |
H A D | smmu_v3_transl.cc | 193 bool hit = ifcTLBLookup(yield, tr, wasPrefetched); local 194 if (!hit) { 195 while (!hit && hazard4kCheck()) { 197 hit = ifcTLBLookup(yield, tr, wasPrefetched); 202 // - there was a TLB hit and the entry was prefetched, OR 204 if (hit) { 329 "micro TLB hit vaddr=%#x amask=%#x sid=%#x ssid=%#x paddr=%#x\n", 362 "SLAVE Interface TLB hit vaddr=%#x amask=%#x sid=%#x ssid=%#x " 395 "SMMU TLB hit vaddr=%#x amask=%#x asid=%#x vmid=%#x paddr=%#x\n", 523 DPRINTF(SMMUv3, "Config hit si [all...] |
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